Periodic Reporting for period 1 - XMem (All-around encapsulated Xene membranes for integration in transistors)
Berichtszeitraum: 2022-06-01 bis 2023-11-30
Silicon is the building block of the transistor, the fundamental unit that drives modern electronic devices from high-performance microchips to low-power and flexible electronics. As consumers, we have directly experienced the meaning of the “Moore’s law”, which predicted the doubling in speed and processing power of electronic systems every two years. However, in the last 5 years Moore’s predictions have been challenged by the laws of solid-state physics, as there is a limit on how small a transistor can be made on silicon. Silicon at the two-dimensional (2d) level, namely silicene, would bring outstanding benefits in terms of extreme size down-scaling, device performance, and flexibility. Two application scenarios showcase the potential impact in this respect:
‒ Transistors in solid-state electronics. Field Effect Transistors (FET) scaling is closely ending up to the physical limit of the single-atom layer.
‒ Low power & flexible electronics. A paradigmatic layout in this field is the thin-film transistor (TFT) that is broadly utilized in the backplane of flat panel displays, flexible and wearable electronics, and sensing devices.
We propose to address the silicon downscaling challenge by introducing silicene, a two-dimensional (2d) form of silicon with graphene-like structure. Silicene is made possible by epitaxy on structurally matched substrates like silver, and as such it is the frontrunner of the emerging class of 2d Xenes [1]. Silicene has the twofold advantage of being ultimately thin (thickness ≤ 0.7 nm as a single layer) due to its 2d nature, and it is inherently structured in a nearly hexagonal layout thus giving it a superior electrical performance that is not vulnerable to charge mobility degradation as in conventional nanoscaled silicon. Silicene proved field effect mobility µ > 100 cm2/Vs, which can be further improved by process optimization, but is not chemically stable on its own. Our recent advances in the ERC-COG Grant. N. 772261 XFab project enable us to recast silicene in a stabilized substrate-free membrane , thus making it compliant with application and integration paths in durable (rigid and/or flexible) device platforms out of the synthesis environment.
‒ Transistors in solid-state electronics. Field Effect Transistors (FET) scaling is closely ending up to the physical limit of the single-atom layer.
‒ Low power & flexible electronics. A paradigmatic layout in this field is the thin-film transistor (TFT) that is broadly utilized in the backplane of flat panel displays, flexible and wearable electronics, and sensing devices.
We propose to address the silicon downscaling challenge by introducing silicene, a two-dimensional (2d) form of silicon with graphene-like structure. Silicene is made possible by epitaxy on structurally matched substrates like silver, and as such it is the frontrunner of the emerging class of 2d Xenes [1]. Silicene has the twofold advantage of being ultimately thin (thickness ≤ 0.7 nm as a single layer) due to its 2d nature, and it is inherently structured in a nearly hexagonal layout thus giving it a superior electrical performance that is not vulnerable to charge mobility degradation as in conventional nanoscaled silicon. Silicene proved field effect mobility µ > 100 cm2/Vs, which can be further improved by process optimization, but is not chemically stable on its own. Our recent advances in the ERC-COG Grant. N. 772261 XFab project enable us to recast silicene in a stabilized substrate-free membrane , thus making it compliant with application and integration paths in durable (rigid and/or flexible) device platforms out of the synthesis environment.
The R&D methodology will rely on the following pillars:
1) Materials synthesis.It will be performed by epitaxy of silicene-stanene (Xene) heterostructures on Ag-based substrates as developed in the XFab project. Testing the quality and reproducibility of the synthesized materials will be carried out and stated in a protocol scheme. Expected deliverable: Product #1 (silicene-on-native-substrate).
2) Materials processing. Stabilized silicene will be disassembled from its native substrate through wet and/or dry delamination schemes as developed in the XFab project. Best schemes will be discerned based on the silicene uniformity and production yield. Expected deliverable: Product #2 (silicene membrane) and #3 (silicene-on-target-substrate).
3) Device prototyping & testing. Stabilized silicene will be integrated in transistor structures supported by SiO2/Si wafer substrates as a gate reference and designed on different length scales to check the scaling metrics of the silicene transistor characteristics. Testing of the prototype will be carried in a lab environment, and then efforts will be undertake to transfer the technology-in-lab to a technology in a relevant environment (e.g. pilot-line of R&D hubs or fabs) after survey with the potential stakeholders. Expected deliverable: proof of stabilized silicene transistors in lab and transfer to a technology relevant environment. A relevant feature of the silicene samples in vie of applications like haptic and strain sensor devices is the piezoresistive effect tested on silicene membranes.
1) Materials synthesis.It will be performed by epitaxy of silicene-stanene (Xene) heterostructures on Ag-based substrates as developed in the XFab project. Testing the quality and reproducibility of the synthesized materials will be carried out and stated in a protocol scheme. Expected deliverable: Product #1 (silicene-on-native-substrate).
2) Materials processing. Stabilized silicene will be disassembled from its native substrate through wet and/or dry delamination schemes as developed in the XFab project. Best schemes will be discerned based on the silicene uniformity and production yield. Expected deliverable: Product #2 (silicene membrane) and #3 (silicene-on-target-substrate).
3) Device prototyping & testing. Stabilized silicene will be integrated in transistor structures supported by SiO2/Si wafer substrates as a gate reference and designed on different length scales to check the scaling metrics of the silicene transistor characteristics. Testing of the prototype will be carried in a lab environment, and then efforts will be undertake to transfer the technology-in-lab to a technology in a relevant environment (e.g. pilot-line of R&D hubs or fabs) after survey with the potential stakeholders. Expected deliverable: proof of stabilized silicene transistors in lab and transfer to a technology relevant environment. A relevant feature of the silicene samples in vie of applications like haptic and strain sensor devices is the piezoresistive effect tested on silicene membranes.
Silicene holds outstanding promises for future electronics as far as it encompasses dimensional reduction down to the 2d level, intrinsically high carrier conduction and low operational power due to its graphene-like structure. The XMem medium-term goal is to standardize silicene production by ensuring process stabilization, reproducibility, and scalability, as well as by testing a durable and reliable performance in prototypical devices. This will enable us to achieve a scale-up of the silicene production beyond the lab level, and then prompt commercialization of silicene standards for the first time. As such, the integration of silicene into a circuitry platform can lead to concrete breakthroughs in the following real-life applications:
‒ Solid-state electronics, to address the More-than-Moore scaling roadmap [3,4] through an atomically thin body thickness for future technology nodes (5 nm and beyond), leakage reduction, better electrostatic control, high mobility, lower power operation, and increased energy efficiency.
‒ Low-power electronics in TFT or strain sensor applications for wearable devices, showing superior performance over the benchmark (see Tab. 1) almost zero-leakage, large-scale uniformity, high degree of mechanical flexibility, and substantial reduction in power consumption.
‒ Quantum technologies for the extreme geometrical confinement.
‒ Energy technologies based on advanced thermoelectric nanomaterials.
XMem may also lead to market innovation by releasing three different silicene products (see Fig. 2) with the following features:
‒ large-area and durable silicene samples (size: 1x1 cm2, i.e. similar to synthetic graphene standards on the market);
‒ scalable production of silicene membranes beyond the research scope;
‒ silicene tested in transistor/piezoresistor devices.
The XMem technology aims to become a building block for next generation electronic devices, having 3 different and progressively more complex and ambitious applications: 1) as a core material for research applications, 2) integrated in a target substrate for the semiconductor industry, and 3) integrated in a transistor for compact and flexible electronics. Piezoresistivity of the so-derived silicene membranes is takes as a figure of merits to assess further exploitation as strain sensor in practical applications. The feasibility of this “lab-to-fab” transition will be evaluated for these 3 scenarios using a “design thinking” approach.
According to the IPR policy, the goal is to ensure that we have the Freedom to Operate (FTO) in the target markets. In terms of FTO, at the date of writing this proposal we have carried out a preliminary assessment on prior art that could possibly hinder the market access, which ensures the clearance to operate on the market with our innovation. During the project we will continue searching for third party patents/patent applications protecting core elements that are strategic for our applications. The strategy aims at identifying these potential deadlocks as soon as possible, with the aim of suggesting to the R&D team the need for alternative development pathways. Besides, a patentability analysis will be carried out to decide whether to file patents to protect the most critical IP.
‒ Solid-state electronics, to address the More-than-Moore scaling roadmap [3,4] through an atomically thin body thickness for future technology nodes (5 nm and beyond), leakage reduction, better electrostatic control, high mobility, lower power operation, and increased energy efficiency.
‒ Low-power electronics in TFT or strain sensor applications for wearable devices, showing superior performance over the benchmark (see Tab. 1) almost zero-leakage, large-scale uniformity, high degree of mechanical flexibility, and substantial reduction in power consumption.
‒ Quantum technologies for the extreme geometrical confinement.
‒ Energy technologies based on advanced thermoelectric nanomaterials.
XMem may also lead to market innovation by releasing three different silicene products (see Fig. 2) with the following features:
‒ large-area and durable silicene samples (size: 1x1 cm2, i.e. similar to synthetic graphene standards on the market);
‒ scalable production of silicene membranes beyond the research scope;
‒ silicene tested in transistor/piezoresistor devices.
The XMem technology aims to become a building block for next generation electronic devices, having 3 different and progressively more complex and ambitious applications: 1) as a core material for research applications, 2) integrated in a target substrate for the semiconductor industry, and 3) integrated in a transistor for compact and flexible electronics. Piezoresistivity of the so-derived silicene membranes is takes as a figure of merits to assess further exploitation as strain sensor in practical applications. The feasibility of this “lab-to-fab” transition will be evaluated for these 3 scenarios using a “design thinking” approach.
According to the IPR policy, the goal is to ensure that we have the Freedom to Operate (FTO) in the target markets. In terms of FTO, at the date of writing this proposal we have carried out a preliminary assessment on prior art that could possibly hinder the market access, which ensures the clearance to operate on the market with our innovation. During the project we will continue searching for third party patents/patent applications protecting core elements that are strategic for our applications. The strategy aims at identifying these potential deadlocks as soon as possible, with the aim of suggesting to the R&D team the need for alternative development pathways. Besides, a patentability analysis will be carried out to decide whether to file patents to protect the most critical IP.