NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS

Projektinformationen

NEUROPULS

ID Finanzhilfevereinbarung: 101070238

DOI

10.3030/101070238

EK-Unterschriftsdatum 24 November 2022

Startdatum 1 Januar 2023

Enddatum 31 Dezember 2027

Finanziert unter

• Digital, Industry and Space

Gesamtkosten

€ 8 319 510,00

EU-Beitrag

€ 8 319 510,00

Koordiniert durch

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS
France

Periodic Reporting for period 2 - NEUROPULS (NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS)

Berichtszeitraum: 2024-01-01 bis 2025-06-30

Zusammenfassung vom Kontext und den Gesamtzielen des Projekts

The growing need to transfer massive amounts of data among multitudes of interconnected devices for e.g. self-driving vehicles, IoT or industry 4.0 has led to a quest towards low-power and secure approaches to locally processing data. Neuromorphic computing, a brain-inspired approach, addresses this need by radically changing the processing of information. Although neuromorphic electrical computing systems offer advantages in terms of CMOS implementations and scalability, they inherit limitations of conventional electronics such as low energy-efficiency, high latency and low bandwidth density. Besides, such systems often require robust security layers for e.g. safety-critical applications. Security layers based on memory-stored secret keys are prone to several types of memory-accessing attacks. Therefore, silicon hardware approaches for security primitives such as physical unclonable functions (PUFs) are currently investigated because of their absence of long-term digital memory storage. Although electronic PUFs have received major attention thanks to their native CMOS implementation, for secure authentication they are prone to machine learning and side-channel attacks due to their CMOS technology.
The NEUROPULS project aims to build next-generation low-power and secure edge-computing systems by developing novel photonic computing architectures and security layers based on photonic PUFs in augmented silicon photonics CMOS-compatible platforms. The integration of emerging non-volatile phase change materials for synapses/neurons and III-V materials for on-chip spiking sources, for the first time, will allow to build novel neuromorphic accelerators featuring RISC-V compliant interfaces for smooth adoption and programmability. Optimal performance will be achieved thanks to a novel full-system simulation platform for design space exploration. Three relevant use-cases will be considered for benchmarking to demonstrate two orders of magnitude energy efficiency improvement.

Arbeit, die ab Beginn des Projekts bis zum Ende des durch den Bericht erfassten Berichtszeitraums geleistet wurde, und die wichtigsten bis dahin erzielten Ergebnisse

Activities performed have focused on most of the main axes of the project. More specifically, they have addressed the development of: (i) the augmented silicon photonics platform, (ii) novel photonic devices based on phase-change materials (PCMs) and related modeling, (iii) architectures for computing and for security layers, (iv) novel security metrics and protocols, (v) a gem5-based simulation platform, and (vi) methodologies for use-cases benchmarking.
From a technological point of view, the GeSe PCM that was chosen after optical testing, has been integrated in the silicon photonics platform. The fabrication of the full process is still in progress.
To handle the multi-physics character of photonic devices based on PCMs, multiple functionalities have been added to the software under development to deal with statistical properties of PCM phase dynamics.
Then, novel photonic designs based on electrically-actuated PCMs have been developed to enable multi-level operation at ultra-low insertion losses.
The architecture of the computing platform encompassing the RISC-V processor and interfaces compatible with the photonic accelerator was finalized and an API has been developed in order to communicate between the RISC-V core and the photonic accelerator. Peripheral circuitry has also been developed in order to allow interfacing between the photonic PIC and the controlling FPGA.
Security protocols based on mutual authentication and remote software attestation leveraging the high speed of operation of PUFs have been refined as well as the investigation of the robustness of photonic PUFs in terms of temperature stability, noise, and ML attacks.
To model the power consumption, latency, and compute density of the accelerator and of its security layers, a dedicated gem5-based simulation platform has been further developed adding new functionalities as well as compatibility with photonic accelerators. The platform can handle co-integration of electronic and photonic systems with RISC-V interfaces.
Benchmarking methodologies for accurate modeling of the NEUROPULS accelerator have been refined.

Fortschritte, die über den aktuellen Stand der Technik hinausgehen und voraussichtliche potenzielle Auswirkungen (einschließlich der bis dato erzielten sozioökonomischen Auswirkungen und weiter gefassten gesellschaftlichen Auswirkungen des Projekts)

From the technological point of view, a figure-of-merit (FOM) deltaN/deltaK close to 170 for the optical bulk properties of GeSe has been achieved experimentally.
The novel photonic devices based on this material can allow record low losses (below 1 dB) for interferometers capable of achieving a full 2pi phase shift swing required for the computing architectures.
The novel designs for matrix multiplication cores based on these devices require fewer components, at the expense of being less generic. Such reduction jointly with lower optical losses allows to achieve a greater scalability in terms of number of layers.
The novel designs of photonic physical unclonable functions (PUFs) do not rely on large input powers to trigger optical non-linearities, while being CMOS-compatible and allowing for anti-tampering ASIC integration.
The novel lightweight authentication and attestation protocols leveraging photonic PUFs (capable to generate CRPs with Gbit/s speeds) provide higher strength to various types of attacks e.g. modeling compared to SoA protocols based on PUFs and requiring to store a large database of CRPs on the verifier side.
The architecture developed, based on a RISC-V processor is an efficient low-cost solution to interface with the photonic device. A dedicated high-speed interface is under development for communication with the photonic devices.
The simulation platform under development can support RISC-V cores and related interfaces and allows for generic electronic-photonic modeling by using design specific accelerators.

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