Description du projet
La première infrastructure européenne de serveurs en nuage RISC-V
L’architecture révolutionnaire de jeu d’instructions (instruction set architecture, ISA) connue sous le nom de RISC-V n’est pas nouvelle. Cette ISA libre et gratuite a été développée il y a plus de dix ans. Toutefois, un nouvel élan se dessine. RISC-V reste attrayante parce que sa licence est gratuite et qu’elle ne comporte que quelques instructions dans l’architecture de base. Dans ce contexte, le projet RISER, financé par l’UE, développera la première infrastructure européenne de serveurs en nuage RISC-V. Le projet intégrera des composants à faible consommation d’énergie dans une architecture en nuage innovante et économe en énergie. Il concevra une plate-forme d’accélération, qui comprendra le processeur Rhea d’EPI, basé sur la technologie Arm, et une carte d’accélérateur PCIe, ainsi qu’une plate-forme de microserveur, qui interconnectera jusqu’à 10 cartes de microserveur, chacune prenant en charge jusqu’à quatre puces RISC-V associées à un stockage et à un réseau à grande vitesse.
Objectif
Building on top of outcomes from the EPI and EUPilot projects, RISER will develop the first all-European RISC-V cloud server infrastructure, significantly enhancing Europe's open strategic autonomy. RISER will leverage and validate open hardware high-speed interfaces combined with a fully-featured operating system environment and runtime system, enabling the integration of low-power components, including the RISC-V processor chips from EPI and EUPilot and LPDDR4 memories, in a novel energy-efficient cloud architecture.
RISER brings together a set of 7 partners from industry and academia to jointly develop and validate open-source designs for standardized form-factor system platforms suitable for supporting cloud services. Specifically, RISER will build the following two cloud infrastructures:
(1) An accelerator platform, which includes the ARM-based RHEA processor from EPI and a PCIe acceleration board that will be developed within the project which will integrate up-to four RISC-V based EPI and EUPilot chips.
(2) A microserver platform, which interconnects up to ten microserver boards all developed by the project, each one supporting up to four RISC-V chips coupled with high-speed storage and networking. Embracing hyperconvergence, the microserver architecture will allow for distributed storage and memory to be used by any processor in the system with very low overhead.
The open-source system board designs of RISER will also be accompanied by open-source low-level firmware and systems software, and a representative Linux-based software stack to support cloud services. To evaluate and demonstrate the capabilities of the RISER platforms we will develop three use cases: (a) Acceleration of compute workloads, (b) Networked object and key-value storage, and (c) Containerized execution as part of a provider-managed IaaS environment. RISER will offer open access to the microserver platform, facilitating uptake and enhancing the commercialization path of project results.
Champ scientifique
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Programme(s)
Régime de financement
HORIZON-RIA - HORIZON Research and Innovation ActionsCoordinateur
70013 Irakleio
Grèce