Periodic Reporting for period 1 - RISER (RISC-V for Cloud Services)
Berichtszeitraum: 2023-01-01 bis 2024-06-30
Building on top of outcomes from the EPI and EUPilot projects, RISER will develop the first all-European RISC-V cloud server infrastructure, significantly enhancing Europe's open strategic autonomy. RISER will leverage and validate open hardware high-speed interfaces combined with a fully-featured operating system environment and runtime system, enabling the integration of low-power components, including the RISC-V processor chips from EPI and EUPilot and LPDDR4 memories, in a novel energy-efficient cloud architecture. RISER brings together a set of 7 partners from industry and academia to jointly develop and validate open-source designs for standardized form-factor system platforms suitable for supporting cloud services. Specifically, RISER will build the following two cloud infrastructures: (1) An accelerator platform, which includes the ARM-based RHEA processor from EPI and a PCIe acceleration board that will be developed within the project which will integrate up-to four RISC-V based EPI and EUPilot chips. (2) A microserver platform, which interconnects up to ten microserver boards all developed by the project, each one supporting up to four RISC-V chips coupled with high-speed storage and networking. Embracing hyperconvergence, the microserver architecture will allow for distributed storage and memory to be used by any processor in the system with very low overhead. The open-source system board designs of RISER will also be accompanied by open-source low-level firmware and systems software, and a representative Linux-based software stack to support cloud services. To evaluate and demonstrate the capabilities of the RISER platforms we will develop three use cases: (a) Acceleration of compute workloads, (b) Networked object and key-value storage, and (c) Containerized execution as part of a provider-managed IaaS environment. RISER will offer open access to the microserver platform, facilitating uptake and enhancing the commercialization path of project results.
In its first 18 months of activity (January 2023-September 2024), the RISER consortium has completed the following essential steps in the project timeline:
- Elaboration of the main requirements for the development of the project’s two system platforms (acceleration card and microserver), in support of the project’s three use cases (acceleration, networked storage, container runtime). This work is reported in Deliverable D2.1 ("Use Cases and Requirements"), submitted in M4.
- Specification of the crucial elements of the architecture, identifying viable implementation options as well. This work is Deliverable “D2.2: Specifications and architecture design", submitted in M7. The technical topics covered include: SoC characteristics, boot/initialization firmware, PCIe characteristics and configuration options, connectivity via high-speed serial links, non-volatile memory/storage, and board/system management. Moreover, D2.2 includes essential specifications for the system software environment. For the accelerator form factor, the RISER software environment is to support the OpenMP programming model, particularly the OpenMP target offload model. The RISER project aims to further enhance this model with support with multiple devices. The functionality and efficiency of this system software environment will be validated with the Accelerator-focused use case. For the Microserver form factor, the RISER system software environment is to support effective integration with the management and monitoring infrastructure of cloud data centers. The functionality and efficiency of this system software environment will be validated with the Networked Object Store and Containers use cases.
- Achievement of Milestone 1 ("Requirements captured & Architecture defined"), having completed a comprehensive architecture design phase that resulted in a set of specification clauses to guide the project’s follow-up effort towards implementation
- Achievement of Milestone 2 ("FPGA emulation completed and verified against specifications"), having completed the implementation of a FPGA-based emulation environment and assorted tools and testsuites software aimed towards ongoing verification and quality evaluation criteria for platform designs, with the purpose of enabling ongoing checks for conformance of the project’s system designs to specifications.
- Elaboration of the main requirements for the development of the project’s two system platforms (acceleration card and microserver), in support of the project’s three use cases (acceleration, networked storage, container runtime). This work is reported in Deliverable D2.1 ("Use Cases and Requirements"), submitted in M4.
- Specification of the crucial elements of the architecture, identifying viable implementation options as well. This work is Deliverable “D2.2: Specifications and architecture design", submitted in M7. The technical topics covered include: SoC characteristics, boot/initialization firmware, PCIe characteristics and configuration options, connectivity via high-speed serial links, non-volatile memory/storage, and board/system management. Moreover, D2.2 includes essential specifications for the system software environment. For the accelerator form factor, the RISER software environment is to support the OpenMP programming model, particularly the OpenMP target offload model. The RISER project aims to further enhance this model with support with multiple devices. The functionality and efficiency of this system software environment will be validated with the Accelerator-focused use case. For the Microserver form factor, the RISER system software environment is to support effective integration with the management and monitoring infrastructure of cloud data centers. The functionality and efficiency of this system software environment will be validated with the Networked Object Store and Containers use cases.
- Achievement of Milestone 1 ("Requirements captured & Architecture defined"), having completed a comprehensive architecture design phase that resulted in a set of specification clauses to guide the project’s follow-up effort towards implementation
- Achievement of Milestone 2 ("FPGA emulation completed and verified against specifications"), having completed the implementation of a FPGA-based emulation environment and assorted tools and testsuites software aimed towards ongoing verification and quality evaluation criteria for platform designs, with the purpose of enabling ongoing checks for conformance of the project’s system designs to specifications.
Results will be reported in detail at a later stage in the project. Currently (time of RV2 review meeting - Sept'2024) the RISER project has achieved preliminary demonstrations of its two main outcomes: Accelerator device, and Microserver - both based on RISC-V open standards, and aiming for use in data center environments.The demonstrations use a FPGA emulation environment developed by the RISER project, synthesizing contributions from partners.