Together for RISc-V Technology and ApplicatioNs

Informazioni relative al progetto

TRISTAN

ID dell’accordo di sovvenzione: 101095947

DOI

10.3030/101095947

Data della firma CE 27 Novembre 2022

Data di avvio 1 Dicembre 2022

Data di completamento 30 Novembre 2025

Finanziato da

• Digital, Industry and Space

Costo totale

€ 53 724 230,31

Contributo UE

€ 15 430 543,81

Coordinato da

NXP SEMICONDUCTORS GERMANY GMBH
Germany

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Documents, reports (7)

Design Specifications of demonstrators
Stakeholder Engagement Plan

Stakeholder Engagement Plan.

Initial requirements architectural map of the demonstrators

Initial requirements architectural map of the demonstrators.

Preliminary integration Report
Intermediate requirements architectural map of the demonstrators
Initial requirements and feedback for SW and EDA Tools IPs

Initial requirements and feedback for SW and EDA Tools IPs.

Initial requirements and feedback for processor and hardware IPs

Development of initial requirements and feedback for processor and hardware IPs.

Data sets, microdata, etc (1)

Intermediate virtual repository and coupling to OpenHWG repository created

Intermediate virtual repository and coupling to OpenHWG repository created.

Other (2)

EDA framework for RISC-V - prototype, report, Open-Source
All governance boards installed

All governance boards installed.

Pubblicazioni

Conference proceedings (13)

SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story

Autori: Gabriele Magnani, Daniele Cattaneo, Lev Denisov, Giuseppe Tagliavini, Giovanni Agosta, Stefano Cherubin
Pubblicato in: Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
Editore: ACM
DOI: 10.1145/3649153.3649203

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Autori: Michael Rogenmoser, Luca Benini
Pubblicato in: 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2024
Editore: IEEE
DOI: 10.1109/ICECS58634.2023.10382727

Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber

Autori: Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, and Guido Masera
Pubblicato in: Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Editore: ACM
DOI: 10.1145/3587135.3591432

Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives

Autori: Dolmeta, Alessandra; Martina, Maurizio; Masera, Guido
Pubblicato in: 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023
Editore: IEEE
DOI: 10.1109/prime58259.2023.10161780

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs

Autori: Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
Pubblicato in: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Editore: IEEE
DOI: 10.23919/DATE58400.2024.10546511

Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes

Autori: Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi
Pubblicato in: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Editore: IEEE
DOI: 10.23919/DATE58400.2024.10546790

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?

Autori: Bruno Endres Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis, Marco Ottavi
Pubblicato in: 2023 IEEE European Test Symposium (ETS), 2023
Editore: IEEE
DOI: 10.1109/ETS56758.2023.10174076

Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs

Autori: Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis, Marco Ottavi
Pubblicato in: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024
Editore: IEEE
DOI: 10.1109/DFT59622.2023.10313556

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Autori: Edian B. Annink, Gerard Rauwerda, Edwin Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi
Pubblicato in: 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022
Editore: IEEE
DOI: 10.1109/DFT56152.2022.9962340

PLiNIO: A User-Friendly Library of Gradient-Based Methods for Complexity-Aware DNN Optimization

Autori: D. Jahier Pagliari, M. Risso, B. A. Motetti and A. Burrello
Pubblicato in: 2023 Forum on Specification & Design Languages (FDL), 2023, ISSN 1636-9874
Editore: IEEE
DOI: 10.1109/FDL59689.2023.10272045

HPDcache

Autori: César Fuguet
Pubblicato in: Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023, ISSN 1942-3462
Editore: ACM
DOI: 10.1145/3587135.3591413

Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers

Autori: Bruno Forlin, Edian B. Annink, Elijah Cishugi, Carlo Cazzaniga, Paolo Rech, Gerard Rauwerda, Gianluca Furano, Marco Ottavi
Pubblicato in: 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2024
Editore: IEEE
DOI: 10.1109/IOLTS60994.2024.10616084

An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores

Autori: Tijmen T. Smit, Bruno Endres Forlin, Kuan-Hsun Chen, Ioanna Souvatzoglou, Mihalis Psarakis, Marco Ottavi
Pubblicato in: 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024
Editore: IEEE
DOI: 10.1109/DFT63277.2024.10753564

Peer reviewed articles (8)

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Autori: Michael Rogenmoser; Yvan Tortorella; Davide Rossi; Francesco Conti; Luca Benini
Pubblicato in: ACM Transactions on Cyber-Physical Systems, 2023, ISSN 2378-9638
Editore: Association for Computing Machinery
DOI: 10.48550/arxiv.2303.08706

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

Autori: Kari Hepola, Joonas Multanen, Pekka Jääskeläinen
Pubblicato in: IEEE Transactions on Computers, Numero 73, 2024, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TC.2023.3337313

Enhancing Neural Architecture Search with Multiple Hardware Constraints for Deep Learning Model Deployment on Tiny IoT Devices

Autori: A. Burrello, M. Risso, B. A. Motetti, E. Macii, L. Benini and D. J. Pagliari,
Pubblicato in: IEEE Transactions on Emerging Topics in Computing, 2023, ISSN 2168-6750
Editore: IEEE
DOI: 10.1109/TETC.2023.3322033

MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge

Autori: Guella, Flavia; Valpreda, Emanuele; Caon, Michele; Masera, Guido; Martina, Maurizio
Pubblicato in: IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, ISSN 1558-0806
Editore: IEEE
DOI: 10.1109/tcsi.2024.3365952

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

Autori: Nadalini, A; Rutishauser, G; Burrello, A; Bruschi, N; Garofalo, A; Benini, L; Conti, F; Rossi, D
Pubblicato in: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2023, ISSN 2159-3477
Editore: IEEE
DOI: 10.48550/arxiv.2307.01056

Keelhaul: Processor-Driven Chip Connectivity and Memory Map Metadata Validator for Large Systems-on-Chip

Autori: Henri Lunnikivi, Roni Hämäläinen, Timo D. Hämäläinen
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numero 32, 2024, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TVLSI.2024.3454431

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Autori: Ottaviano, Alessandro; Balas, Robert; Bambini, Giovanni; Del Vecchio, Antonio; Ciani, Maicol; Rossi, Davide; Benini, Luca; Bartolini, Andrea
Pubblicato in: International Journal of Parallel Programming, 2023, ISSN 1573-7640
Editore: nternational Journal of Parallel Programming
DOI: 10.21203/rs.3.rs-2525734/v1

<i>Xvpfloat</i>: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Autori: Eric Guthmuller; César Fuguet; Andrea Bocco; Jérôme Fereyre; Riccardo Alidori; Ihsane Tahir; Yves Durand
Pubblicato in: IEEE Transactions on Computers, 2024, ISSN 1557-9956
Editore: IEEE
DOI: 10.1109/tc.2024.3383964

Other (2)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Autori: Francesco Conti; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggiman; Hayate Okuhara; Luca Benini
Pubblicato in: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Editore: IEEE
DOI: 10.48550/arxiv.2305.08415

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Autori: Alessandro Ottaviano; Thomas Benz; Paul Scheffler; Luca Benini
Pubblicato in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, ISSN 1558-3791
Editore: IEEE
DOI: 10.3929/ethz-b-000638551