Periodic Reporting for period 2 - REBECCA (Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI)
Berichtszeitraum: 2023-10-01 bis 2024-07-31
The REBECCA project outlines comprehensive technological and business objectives focused on advancing AI applications. It plans to develop innovative hardware (HW) and software (SW) subsystems integrated into a platform to enhance the efficiency of executing demanding AI applications in real-time, with lower energy consumption, appropriate safety integrity levels, and high security. The project involves designing a chiplet with an advanced RISC-V processor and hardware AI accelerators, utilizing reconfigurable logic for efficient AI application implementation. Two interconnected chiplets will be secured in a silicon package. The SW stack will be enhanced, incorporating a toolset for design space exploration, considering constraints such as cost, performance, energy, safety, and security. Specific safety requirements for different domains, like ISO 26262 for automotive and DO-178C for avionics, will be addressed. Security vulnerabilities will be mitigated through SW and HW hardening modules, alongside a sub-tool for security verification using a model checker. The REBECCA platform will undergo validation and evaluation across dimensions like performance, power consumption, security, and safety, using real-world applications in various domains. The project aims to disseminate results through national and international activities, influencing future edge-AI systems. Adoption of recent interconnectivity and security standards is expected to attract attention from edge/IoT manufacturers, integrators, and developers.
The adoption of REBECCA technologies is poised to revolutionize the European IT industry, introducing a new class of edge-AI hardware and software resources marked by state-of-the-art advancements. These innovations encompass CPUs, AI accelerators, reconfigurable logic, multi-chiplet devices, system software, middleware, and AI frameworks, democratizing access to these resources as a service for SMEs to large organizations. Market research, consortium expertise, and innovation strategies indicate a growing demand for more powerful computing capabilities, aligning with REBECCA's focus on the global Edge AI Market and the Reconfigurable Market. The project aims to deliver a European AIoT node with high-performance, safety, and security within a compact energy envelope. Additionally, REBECCA will provide an advanced HW/SW co-design suite to enhance designers' productivity, incorporating design space exploration tools that consider various constraints from the outset. Optimization of AI algorithms and frameworks will result in a comprehensive hardware and software stack, enabling more efficient execution of AI applications across multiple dimensions, including performance, energy, safety, security, and time-to-market. The development of a REBECCA multi-die chiplet promises improved energy efficiency and processing capabilities for AI tasks. A complete virtualization scheme will allow diverse operating systems and middleware to run securely on REBECCA hardware modules, catering to applications from different domains. Importantly, REBECCA's holistic design approach prioritizes security, reliability, and safety, with design space exploration tools incorporating constraints for application in critical sectors, offering a novel paradigm for these domains.
The adoption of REBECCA technologies is poised to revolutionize the European IT industry, introducing a new class of edge-AI hardware and software resources marked by state-of-the-art advancements. These innovations encompass CPUs, AI accelerators, reconfigurable logic, multi-chiplet devices, system software, middleware, and AI frameworks, democratizing access to these resources as a service for SMEs to large organizations. Market research, consortium expertise, and innovation strategies indicate a growing demand for more powerful computing capabilities, aligning with REBECCA's focus on the global Edge AI Market and the Reconfigurable Market. The project aims to deliver a European AIoT node with high-performance, safety, and security within a compact energy envelope. Additionally, REBECCA will provide an advanced HW/SW co-design suite to enhance designers' productivity, incorporating design space exploration tools that consider various constraints from the outset. Optimization of AI algorithms and frameworks will result in a comprehensive hardware and software stack, enabling more efficient execution of AI applications across multiple dimensions, including performance, energy, safety, security, and time-to-market. The development of a REBECCA multi-die chiplet promises improved energy efficiency and processing capabilities for AI tasks. A complete virtualization scheme will allow diverse operating systems and middleware to run securely on REBECCA hardware modules, catering to applications from different domains. Importantly, REBECCA's holistic design approach prioritizes security, reliability, and safety, with design space exploration tools incorporating constraints for application in critical sectors, offering a novel paradigm for these domains.
The main work carried out in the reporting period (Μ9-Μ18) can be summarised as follows.
Development of HW & SW sub-components:
- In M12, the first Alpha version of the HW and SW sub-components of the REBECCA platform, covering RISC-V processing system, ASIC and FPGA accelerators, and chiplet interconnections was developed. (WP2/D2.1 WP3/D3.1)
- In M18, the Beta versions of the REBECCA HW and SW sub-components were developed. (WP2/D2.2 WP3/D3.2)
- Created the intermediate Beta version of the System Software, including operating systems, hypervisors, middleware, orchestration tools, and AI frameworks. (WP3/D3.2)
- Developed the initial version of the processing sub-system and hardware AI accelerators (WP2/D2.2) emulated on a Xilinx Alveo U55C board (WP6/D6.1 not submitted yet)
- Produced the intermediate Beta version of the REBECCA Design Space Exploration tools for advanced design space exploration. (WP4/D4.2)
- Developed and functionally verified the Intrusion Detection System (IDS) module for the REBECCA ASIC on both the U55C and VCU128 demonstrator boards. (WP2/D2.2)
- Work on the REBECCA ASIC/back-end flow has begun with the component providers for it having coordinated discussions on the type of module descriptions that will be provided as well as the tools needed for the flow. (WP2/D2.4 due M34)
System Integration and Emulation platform:
- Created AI/ML accelerators on the Alveo U55C accelerator and started integration with the remaining system. (WP6/D6.1 due M21)
- Ported the processing sub-system on the Xilinx Alveo VCU128 board and extended the design to include a HyperRam controller to access the processor’s main memory. (WP6/D6.1 due M21)
- Worked in collaboration with ETH Zurich to develop an FMC board featuring HyperRam memory, an SD card slot, and debug connectors. This board will interface with the VCU128 to derive the REBECCA emulation environment. (WP6/D6.1 due M21)
Development of HW & SW sub-components:
- In M12, the first Alpha version of the HW and SW sub-components of the REBECCA platform, covering RISC-V processing system, ASIC and FPGA accelerators, and chiplet interconnections was developed. (WP2/D2.1 WP3/D3.1)
- In M18, the Beta versions of the REBECCA HW and SW sub-components were developed. (WP2/D2.2 WP3/D3.2)
- Created the intermediate Beta version of the System Software, including operating systems, hypervisors, middleware, orchestration tools, and AI frameworks. (WP3/D3.2)
- Developed the initial version of the processing sub-system and hardware AI accelerators (WP2/D2.2) emulated on a Xilinx Alveo U55C board (WP6/D6.1 not submitted yet)
- Produced the intermediate Beta version of the REBECCA Design Space Exploration tools for advanced design space exploration. (WP4/D4.2)
- Developed and functionally verified the Intrusion Detection System (IDS) module for the REBECCA ASIC on both the U55C and VCU128 demonstrator boards. (WP2/D2.2)
- Work on the REBECCA ASIC/back-end flow has begun with the component providers for it having coordinated discussions on the type of module descriptions that will be provided as well as the tools needed for the flow. (WP2/D2.4 due M34)
System Integration and Emulation platform:
- Created AI/ML accelerators on the Alveo U55C accelerator and started integration with the remaining system. (WP6/D6.1 due M21)
- Ported the processing sub-system on the Xilinx Alveo VCU128 board and extended the design to include a HyperRam controller to access the processor’s main memory. (WP6/D6.1 due M21)
- Worked in collaboration with ETH Zurich to develop an FMC board featuring HyperRam memory, an SD card slot, and debug connectors. This board will interface with the VCU128 to derive the REBECCA emulation environment. (WP6/D6.1 due M21)
The project is currently in the implementation phase. The REBECCA platform, the main outcome of the project, will be available in the next reporting period. The AI and security accelerators have been developed and will be integrated in WP6 to form the final platform. This will result in the first fully European edge-AI device, aiming to produce significant research outcomes that will influence future EU products and impact the European IoT market.