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Tuning the electronic structure of two-dimensional semiconductor junctions

Periodic Reporting for period 1 - 2D-InTune (Tuning the electronic structure of two-dimensional semiconductor junctions)

Berichtszeitraum: 2023-07-01 bis 2025-06-30

Modern electronics increasingly relies on atomically thin “two-dimensional” (2D) materials whose properties can be tailored by stacking or joining different layers. A central challenge is to control what happens at the interfaces—where charge enters or leaves a 2D layer and where band bending, screening and strain can dramatically change device performance. Reducing contact resistance, achieving stable junctions and preserving the intrinsic properties of the active layer are all essential for energy-efficient, scalable technologies.

This project addresses these needs by combining molecular beam epitaxy (MBE) growth with low-temperature scanning tunnelling microscopy and spectroscopy (STM/STS), low-energy electron diffraction (LEED) and qPlus AFM/KPFM. The overall objective is to establish design rules for 2D junctions at the atomic scale, demonstrated on three model systems: (i) interfacial tuning of MoS2 via controlled self-intercalation at the 2D/metal interface; (ii) MBE-grown lateral MoS2–TaS2 heterojunctions as a route to low-barrier contacts; and (iii) the quasi-freestanding growth of ReS2 on graphene/Ir(111) to access the intrinsic, anisotropic properties of ReS2. Together, these efforts aim to enable reliable, low-power 2D devices and to provide robust, shareable workflows for the wider community.
A unified, ultra-high-vacuum platform was built to grow, verify and measure 2D interfaces without leaving controlled conditions. Standard operating procedures were established (substrate preparation → MBE growth → LEED quality check → low-T STM/STS; optional KPFM for local potential mapping), along with a reproducible data pipeline.

Key technical achievements

Interfacial tuning in MoS2: A self-intercalation route at the MoS2/metal interface was implemented. STS line-scans and maps show systematic shifts of band edges and screening, evidencing controllable band-bending at the interface.

Lateral MoS2–TaS2 heterojunctions (MBE): Sequential growth produced clean lateral junctions. Nanoscale spectroscopy indicates well-aligned bands and low apparent Schottky barriers, relevant for contact engineering.

ReS2 on graphene/Ir(111): High-quality growth was achieved. Atomically resolved STM confirms the characteristic anisotropic lattice, while STS reveals intrinsic electronic features consistent with weak substrate coupling—an excellent platform for direction-dependent optoelectronics.

Methods & validation: qPlus AFM/KPFM (skills consolidated during secondment) provided independent work-function/potential maps across grain boundaries; LEED was calibrated for rapid epitaxy checks; analysis tools for drift-corrected STS profiles, band-edge extraction and uncertainty estimation were implemented. Reproducibility was verified via repeated growth/measurement cycles and reference conditions.
A single, integrated workflow links epitaxial growth, crystallographic verification and atomically resolved spectroscopy/potential mapping, enabling unit-cell-level control of 2D junctions.

In-situ interfacial tuning of MoS2 demonstrates that band alignment and screening can be engineered during fabrication rather than corrected post-hoc.

MBE-grown MoS2–TaS2 lateral heterojunctions display signatures of low barrier behaviour at the nanoscale—an attractive path to lower contact resistance in 2D devices.

Quasi-freestanding ReS2/Gr/Ir(111) offers a clean route to probe and utilise the intrinsic, anisotropic properties of ReS2 for polarization-sensitive optoelectronics.

Indicative impacts

Device-level benefits: Lower effective barriers and controlled band bending support reduced power consumption and improved charge injection in transistors, photodiodes and sensors.

Transferable methodology: The growth–metrology pipeline, along with shareable protocols and analysis code, can be adopted by other labs and adapted to further 2D stacks.

Knowledge base: The project formulates practical design rules for interface engineering in TMD-based junctions, accelerating down-selection of device-ready heterostructures.

Key needs for further uptake

Demonstration: Fabricate and measure prototype devices to confirm low-barrier behaviour under operating conditions (I–V curves, temperature/illumination stability).

Scaling: Optimise growth for larger areas and diverse substrates while preserving interface quality.

Standards & data: Release curated STM/STS datasets with rich metadata; align with community schemas for interoperability and reuse.

IP & translation: Early novelty checks for interface-engineering protocols; where appropriate, defensive publication or patenting; engage SMEs and instrument makers for pilot lines (TRL 3–4).
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