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10 Angstrom CMOS exploration

Project description

Revolutionising semiconductors to improve 10A CMOS chips

Chip design and development are crucial to the innovation and advancement of hardware and software across most sectors. The creation of novel semiconductors, reduced size, and better cost-efficiency can revolutionise the industry. The EU-funded 10ACe project aims to explore and develop novel solutions for advancing the 10A CMOS chip technology. It plans to do so through the collaboration of a consortium spread across the chip’s value chain, aiming to use novel hardware and software to revolutionise semiconductor design, while adhering to Moore’s Law. The consortium will focus on four design pillars: improving lithography equipment, optimising chip and mask design, enhancing processing, and achieving high-throughput process characterisation.

Objective

The objective of the 10ÅCe pThe objective of the 10ÅCe project is to explore and realize solutions for the 10Å CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive.

The 10ÅCe project is built based on the following four pillars.

Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will:
• Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield.
• Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished.

Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will:
• Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area.
• Development of new computational lithography solutions to print 10Å CFET structures, to improve imaging by next generation mask design.

Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will:
• Demonstrate a fully functional monolithic CFET (mCFET)
• Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development.
Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will:
• Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10Å 3D CFET devices, interconnect and materials

Coordinator

ASML NETHERLANDS B.V.
Net EU contribution
€ 2 700 000,00
Address
DE RUN 6501
5504DR Veldhoven
Netherlands

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Region
Zuid-Nederland Noord-Brabant Zuidoost-Noord-Brabant
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
Links
Total cost
€ 13 500 000,00

Participants (30)

Partners (1)