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Training and Innovation in Reliable and Efficient Chip Design for Edge AI

Project description

Addressing Edge AI challenges and training innovators

Artificial intelligence is transforming industries by moving computation to the data source, a concept known as Edge AI. This approach is critical for applications demanding high performance, ultra-low latency, and efficient power use. The EU Chips Act highlights the strategic need for a skilled workforce in this sector. However, Edge AI faces challenges such as limited computing resources, evolving market dynamics, and regulatory uncertainties. With the support of the Marie Skłodowska-Curie Actions programme, the TIRAMISU project aims to develop reliable and energy-efficient Edge AI hardware through interdisciplinary training and innovation management. Collaborating with top universities and industry leaders, TIRAMISU fosters synergies between technical design and innovation management, preparing future European engineers and researchers.

Objective

Artificial intelligence is increasingly being brought to the source of data, thus establishing the Edge AI concept. Edge AI is gaining momentum across various industries and services by public authorities and enables new applications requiring high performance, ultra-low latency with high bandwidth, efficient power use, and intelligence beyond regular computing. Its strategic importance is emphasised through the EU Chips Act monetary investments in the EU semiconductor supply chain, highlighting the urgent need for a qualified workforce. The advancements in Edge AI applications face critical research and engineering challenges related to limited computing and energy resources of the edge devices, limitations of the existing AI algorithms and their insufficient fit. Also, the related rapid technological advancements, market dynamics, interdisciplinarity, and regulatory uncertainty set a unique challenge for the valorisation and management of Edge-AI innovations. The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management.
The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - PUNCH, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.

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Coordinator

TALLINNA TEHNIKAÜLIKOOL
Net EU contribution
€ 477 014,40
Address
EHITAJATE TEE 5
12616 Tallinn
Estonia

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Region
Eesti Eesti Põhja-Eesti
Activity type
Higher or Secondary Education Establishments
Links
Total cost
No data

Participants (8)

Partners (1)