The MoWiLife project has six main objectives. The main achievements are described in relation to these objectives.
Objective O1: 2.3 kV SiC MOSFET module with access to TSEP, self-protection features and high power density
The MoWiLife-SiC-MOSFET module will have advanced self-protection features. This includes protection against high short-circuit currents by a sense-FET, protection against drain-source overvoltage by an module-integrated active clamping circuit and protection against high negative gate-source voltage by an chip-integrated source-gate diode. These features require new SiC-MOSFET chips, which have been developed and fabricated in the first phase of this project. Improved power density is going to be achieved by an improved thermal performance of the module base plate und by use of direct water cooling. Different materials for the base plate have been evaluated. To improve the thermal conductivity between the base plate and the coolant water, ribbon bonds on the base plate backside are going to be used.
Objective O2: Pilot 1 - SiC wind power converter
MoWiLife will demonstrate a 20% power density improvement of a wind power converter by using 2.5 kV SiC-MOSFET modules. A feasibility study has shown that three parallel MOSFET modules are necessary to reach the output power of 2.5 MW. Different possibilities for the stack-layout have been investigated and a preferred solution has been found.
Double pulse tests to evaluate the switching behavior of the SiC-MOSFET, to determine the gate resistances for smooth switching with low switching losses and to measure the switching losses have been performed.
Objective O3: Pilot 2 – SiC converter with condition monitoring
The main idea for condition monitoring in this project is to use the temperature dependence of the MOSFET source-gate diode as temperature sensitive parameter. To read out the temperature, the gate driver feeds a continuous current in the mA range into this diode while the MOSFET is in the off-state. By measuring the on-state voltage of the diode, it’s temperature can be determined. The gate driver with this feature has been designed and fabricated. Besides measuring the diode voltage, this gate driver can also measure the MOSFET on-state voltage during conduction. The information about the on-state voltage is sent back to the converter control. Together with the information about the current, the temperature can be determined. There are two requirements regarding condition monitoring. On the one hand, wear-out has to be detected before the device fails. This is going to be tested in a power cycling test bench. On the other hand, the condition monitoring circuit must be immune against false triggering in an inverter environment with high EMI levels. This is going to be tested in a converter in continuous operation. The power stack of such a converter including condition monitoring has been developed, switching performance of the SiC-MOSFET in this inverter has been tested.
Objective O4: Pilot 3 – SiC-MOSFET medium voltage DC-DC converter
The DC-DC converter should be able to connect a 1.5 kV PV system to a medium voltage collection grid with e.g. 10 kV DC. In the first project phase, a concept study has been performed. A dual active bridge (DAB) converter with parallel connection on the low voltage and series connection on the medium voltage level turned out to be the most favorable solution.
The DAB converter should operate at zero voltage switching. To evaluate the zero voltage switching behavior, a special test setup was realized. A ZVS gate driver has been developed in two versions, as well as a low inductive snubber capacitor board. Switching measurements have been performed, showing the potential of zero voltage switching with unipolar power semiconductors.
Objective O5: Pilot 4 – High Voltage DC Circuit Breaker
The basic 4.8 kV, 5-10 kA hybrid DC CB based on 4 series connected SiC MOSFETs has been designed and simulation model developed on PSCAD. Additionally, 2 other topologies are designed: 9 kV, 5-10 kV to test scaling to higher voltages, and 4.8 kV, 10-15 kV topology to test scaling to higher currents. In the first phase of the project, also more detailed SPICE model has been developed for SiC MOSFET to enable studies of detailed transients and series connection. In addition, the test bench for high voltage, high current tests has been upgraded.
Objective O6: Pilot 4 – Feasibility of Ultra-Wide Bandgap 20 kV FET
The high critical electric field of diamond opens the potential of unipolar devices with a much higher blocking voltage than SiC ones. In comparison to SiC devices, the drift layer thickness will be much lower. But compared to today’s diamond semiconductor samples with a blocking voltage around 1 kV, the drift layer has to be more than factor 10 higher. Therefore, growing of thick diamond layers and diamond deep etching are crucial technologies for ultra-high voltage devices. Remarkable progress was made in both areas during the first phase of the project. For example, growing of 10 µm-thick diamond layers with a very uniform thickness and low surface roughness was achieved. Diamond deep etching was increased from 5 µm to 20 µm.
