The result is a testability methodology and corresponding set of testability tools for use in the development of VHDL code. The testability methodology allows the designer to work with different levels of abstraction using appropriate techniques. The methodology and supporting testability tools have proved to be highly effective in terms of performance and reducing time for design recycle.
The testability methodology defined, and the corresponding set of testability tools developed, allow the designer to take into account the problem of design testability from the entry-level of abstraction, without waiting for the gate-level description, where the solution to any testability problem heavily affects the other important design parameters such as area and performance.
The testability methodology defined allows the designer to start from the behavioral VHDL description, thus identifying a level of testability measured as the expected gate-level fault coverage. This measure has been shown to be very close to the actual gate-level one. The designer is also able to identify redundant VHDL code and the VHDL parts which are more difficult to test, thus allowing the specification to be modified.
Whenever the behavioural level is not available, but the design entry is an RT-level VHDL code, the methodology analyses separately the control part and the data part, applies different analysis techniques to identify the hard to test VHDL points, and provides possible functional design for testability solutions based on a partial scan-type approach.
Finally, at gate level, test generation and redundancy removal tools for interacting finite state machines are provided, thus complementing the commercial test pattern generators available on the market, which are not able to efficiently deal with complex interacting finite state machines. The overall methodology has proved to be very effective in terms of size of designs analyzed, time saved avoiding design re-cycles, and results in terms of area and performance after the application of the proposed functional design for testability techniques. It is under test by the Italian telecom manufacturer which provided some of the benchmarks.
Project URL : http://babbage.informatik.uni-oldenburg.de/research/request.html