Final Report Summary - NANOSYS (Nanosystems: Architectures, Design and Applications)
The broad objective of this research is to study nano-devices, nanocircuits, nanosystem architectures and design tools which provide us with an alternative to CMOS for realizing computational systems as well as their interaction with the biological environment. In particular this project has been focusing on Silicon Nanowire (SiNW) device primitives for computational components and on both SiNW and Carbon Nanotube (CNT) nanostructured sensors for electro-bio interfaces. The grant has enabled the design and fabrication of both nano computing and sensing devices with unique properties.
We have investigated the design and fabrication of controlled-polarity SiNW transistors. The fully-functional fabricated devices are based on vertically-stacked gate-all-around SiNW structures. These devices have two gates and programmable polarity, as predicated by the numerical device simulation, where one gate controls carrier type (p/n) by electrostatic means while the other gate controls the conduction (yes/no) in the SiNW channels. This feature makes the device more expressive in terms of logic as compared to standard technologies (e.g. CMOS), thus leading to higher computational density. We have fabricated simple logic gates, such inverters, NAMNDs, NORs and EXORs and we have shown the correct and predicted operation in silicon.
Next we have investigated architectural templates for nanosystems based on SiNW, and we have concentrated on a regular gate-array style arrangement, to insure predictable routing and corresponding wiring delay. We have shown how logic cells based on SiNW can be arranged as arrays of tiles, the tiles being programmable at the mask level by local interconnect. We also investigated algorithms for the physical design of these tiles, and for the transistor arrangement with each tile. The algorithms were programmed into a CAD tool, and inserted into a full design flow.
We have also researched both thermal and signal integrity issues in 3-dimensional (3D) integrated circuits based on stacking dies with TSVs. In parallel, we have investigated - in conjunction with CEA/LETI in France - monolithic 3D integration. In particular, we have studied a means of designing logic gate layouts on two adjacent levels, i.e. with superimposed MOS transistors. We have developed physical design tools for partitioning, folding and routing logic cells within monolithic 3D integration.
We have investigated further networks on chips (NoCs) for 2D and 3D circuits. A specific contribution addressed the use of NoCs to support wide-I/O in 3D systems. Another contribution addressed the use of NoCs to support cache coherence in servers.
We have studied fabrication-induced variations for SiNW as well as methods to measure and mitigate the variability. Our methodology combines TCAD simulations with a learning algorithm to create a compact parameterized model, and takes into account the nonlinearity among fabrication process and performance parameters that is necessary for high-precision variation analysis. We studied manufacturing defects and ways of capturing them through fault models, which depart from the classical fault model for CMOS to take into account the variable polarity of the transistors.
Finally, we have investigated means of realizing electronic bio-interfaces, i.e. bio-sensors for metabolites (e.g. glucose, lactate, etc.) as well as drugs (e.g. naproxen, paracetamol, etc.) that can be used by an implanted nanosystem to acquire information from a hosting animal (or human) body. We have fabricated and successfully tested sensors base on nano-structuring electrodes with both SiNW and carbon nanotubes (CNTs) and we have shown that we are able to achieve higher performance (in terms of sensitivity and limit of detection) as compared to state of the art biosensors.
As demonstrators of the overall technology we have constructed two implantable and programmable biosensisng systems. These systems are 3-Dimensional integrated circuits, housing sensing, data processing and transmission, as well as energy harvesting. An implant has been successfully tested in freely-moving animal models, thus showing the combined value of the proposed research objectives.
We have investigated the design and fabrication of controlled-polarity SiNW transistors. The fully-functional fabricated devices are based on vertically-stacked gate-all-around SiNW structures. These devices have two gates and programmable polarity, as predicated by the numerical device simulation, where one gate controls carrier type (p/n) by electrostatic means while the other gate controls the conduction (yes/no) in the SiNW channels. This feature makes the device more expressive in terms of logic as compared to standard technologies (e.g. CMOS), thus leading to higher computational density. We have fabricated simple logic gates, such inverters, NAMNDs, NORs and EXORs and we have shown the correct and predicted operation in silicon.
Next we have investigated architectural templates for nanosystems based on SiNW, and we have concentrated on a regular gate-array style arrangement, to insure predictable routing and corresponding wiring delay. We have shown how logic cells based on SiNW can be arranged as arrays of tiles, the tiles being programmable at the mask level by local interconnect. We also investigated algorithms for the physical design of these tiles, and for the transistor arrangement with each tile. The algorithms were programmed into a CAD tool, and inserted into a full design flow.
We have also researched both thermal and signal integrity issues in 3-dimensional (3D) integrated circuits based on stacking dies with TSVs. In parallel, we have investigated - in conjunction with CEA/LETI in France - monolithic 3D integration. In particular, we have studied a means of designing logic gate layouts on two adjacent levels, i.e. with superimposed MOS transistors. We have developed physical design tools for partitioning, folding and routing logic cells within monolithic 3D integration.
We have investigated further networks on chips (NoCs) for 2D and 3D circuits. A specific contribution addressed the use of NoCs to support wide-I/O in 3D systems. Another contribution addressed the use of NoCs to support cache coherence in servers.
We have studied fabrication-induced variations for SiNW as well as methods to measure and mitigate the variability. Our methodology combines TCAD simulations with a learning algorithm to create a compact parameterized model, and takes into account the nonlinearity among fabrication process and performance parameters that is necessary for high-precision variation analysis. We studied manufacturing defects and ways of capturing them through fault models, which depart from the classical fault model for CMOS to take into account the variable polarity of the transistors.
Finally, we have investigated means of realizing electronic bio-interfaces, i.e. bio-sensors for metabolites (e.g. glucose, lactate, etc.) as well as drugs (e.g. naproxen, paracetamol, etc.) that can be used by an implanted nanosystem to acquire information from a hosting animal (or human) body. We have fabricated and successfully tested sensors base on nano-structuring electrodes with both SiNW and carbon nanotubes (CNTs) and we have shown that we are able to achieve higher performance (in terms of sensitivity and limit of detection) as compared to state of the art biosensors.
As demonstrators of the overall technology we have constructed two implantable and programmable biosensisng systems. These systems are 3-Dimensional integrated circuits, housing sensing, data processing and transmission, as well as energy harvesting. An implant has been successfully tested in freely-moving animal models, thus showing the combined value of the proposed research objectives.