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Content archived on 2024-05-14

Ultimate integration of silicon

Objective

The aim is to evaluate how far the MOS concept can be scaled down by pushing today's existing state-of-the art CMOS technology. In addition to the classical architecture (lateral bulk MOSFET's), the performances of SOI devices will be evaluated. SOI technology is a good challenger in order to reduce or suppress some major parasitic effects observed in bulk Si MOSFETs and to increase the performance of the devices.

CMOS is the mainstream technology in microelectronics and will remain so early into the 21st century. The 1 Gbit technology generation with feature sizes of 0.18 µm is already under development. The scaling scenario put forth in widely accepted industry roadmaps calls for sub 100-nm MOSFET's within the next 10 years. The design, optimisation, and fabrication of devices with such dimensions pose formidable challenges owing to the technological and physical limits. The ultimate scaling down of the channel length of MOSFET's is probably in the range between 50 to 20 nm. Various technological hurdles must be overcome. Foremost among these are lithography and patterning. All parts of the MOSFET - gate stack, channel and source-drain architectures, metallic contacts - present new problems. Parasitic effects (e.g. short-channel effects, series resistance, reduction in current drive due to high doping) will be exacerbated. Below 50 nm, hitherto unimportant physical effects, such as quantum effects, will begin to emerge.

The present working group consortium proposes a study of the problems related to the fabrication, understanding and optimisation of deep sub-0.1 µm MOSFET's (NMOS and PMOS with channel length in the range of 100 to sub-50 nm).

Fields of science (EuroSciVoc)

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Programme(s)

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Topic(s)

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Funding Scheme

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ACM - Preparatory, accompanying and support measures

Coordinator

Institut National Polytechnique de Grenoble
EU contribution
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Address
Avenue Felix Viallet 46
38031 Grenoble 1
France

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Total cost

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