Final Report Summary - THZPOWERELECTRONICS (Enabling Technologies for High Power Terahertz Electronic Circuitry)
The Terahertz range (300 GHz – 3 THz) of the electromagnetic spectrum is largely unused for the lack of solid-state Terahertz electronic components. Exciting applications can be found in many areas including Communications, Navigation, Security, Material Engineering, and Medical and Life Sciences, owing to the character of Terahertz electromagnetic radiation. Examples of applications are high-bandwidth (>= 100 Gb/s) wireless communication links for next-generation wireless backhaul, campus and in-building mobile networks and wireless access networks, high-resolution RADAR for autonomous machine and robotic applications, imaging of concealed objects, detection of trace substances such as explosives and toxic gases by Terahertz spectroscopy, material defect imaging and analysis, and subcutaneous and dental imaging. To date, the realization of Solid-State Terahertz Electronic Circuits with significant output power remains an unsolved technological challenge. To reach this goal, faster transistors capable of outputting significant power are needed. Indium Phosphide is used as a semiconductor material to realize these extremely fast devices, taking advantage of this material’s unique combination of high electron mobility and velocity along with its high breakdown field. Transistor frequency scaling is accomplished by shrinking optimized high-speed transistors to lateral dimensions below 100 nm. The device development builds on a heterobipolar transistor process which exists at the host institute, with a goal of extending its frequency range from currently 300 GHz towards one Terahertz.
Since the beginning of the project, the basic fabrication steps of transferred substrate InP HBT circuits have been modified to permit integration of deep submicron transistors. In particular, the width and vertical accuracy of interconnect traces and the yield of passive circuit elements such as high-frequency capacitors and resistors have been addressed. The device development itself includes the simulation of electron transport through the vertical layer stack, under consideration of parasitic capacitances and terminal resistances, to predict cutoff frequencies. The design work includes the optimization of layer thickness, doping level, and lateral device extent. The device simulation of scaled InP HBT was successfully set up, using a commercial simulation framework (Silvaco ATLAS). Transistors with 500 and 300 nm emitter width were fabricated with the use of electron beam lithography. Lithography and metal lift-off processes suitable for 300 nm emitter width were developed. Emitter and collector semiconductor structures were scaled down to this size, enabled by the adjustment of wet chemical etch processes. Functioning transistors were characterized both by DC and RF measurement techniques. The measurements indicated an increase of the maximum frequency of oscillation above 450 GHz, compared to the 800 nm wide baseline structures with fmax around 320 GHz. Compared to the first reporting period, the current gain cutoff frequency fT of 500 nm devices was increased to 350 GHz while simultaneously reaching 450 GHz fmax. In the here reported-on second phase of the program, optimization of the epitaxial layer sequence and its dopant profile was continued. In addition, improved ohmic contact recipes for the emitter were implemented. In the program's second phase, analog integrated circuits were realized with the newly developed transistors for the first time. Amplifier circuits with cascode topology were measured, indicating an increase of bandwidth and gain over the baseline technology.
Since the beginning of the project, the basic fabrication steps of transferred substrate InP HBT circuits have been modified to permit integration of deep submicron transistors. In particular, the width and vertical accuracy of interconnect traces and the yield of passive circuit elements such as high-frequency capacitors and resistors have been addressed. The device development itself includes the simulation of electron transport through the vertical layer stack, under consideration of parasitic capacitances and terminal resistances, to predict cutoff frequencies. The design work includes the optimization of layer thickness, doping level, and lateral device extent. The device simulation of scaled InP HBT was successfully set up, using a commercial simulation framework (Silvaco ATLAS). Transistors with 500 and 300 nm emitter width were fabricated with the use of electron beam lithography. Lithography and metal lift-off processes suitable for 300 nm emitter width were developed. Emitter and collector semiconductor structures were scaled down to this size, enabled by the adjustment of wet chemical etch processes. Functioning transistors were characterized both by DC and RF measurement techniques. The measurements indicated an increase of the maximum frequency of oscillation above 450 GHz, compared to the 800 nm wide baseline structures with fmax around 320 GHz. Compared to the first reporting period, the current gain cutoff frequency fT of 500 nm devices was increased to 350 GHz while simultaneously reaching 450 GHz fmax. In the here reported-on second phase of the program, optimization of the epitaxial layer sequence and its dopant profile was continued. In addition, improved ohmic contact recipes for the emitter were implemented. In the program's second phase, analog integrated circuits were realized with the newly developed transistors for the first time. Amplifier circuits with cascode topology were measured, indicating an increase of bandwidth and gain over the baseline technology.
