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Publications

Back-gate bias effect on UTBB-FDSOI non-linearity performance

Author(s): B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, J.-P. Raskin
Published in: 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, Page(s) 148-151
DOI: 10.1109/ESSDERC.2017.8066613

Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs

Author(s): V. Kilchytska, B. Kazemi Esfeh, C. Gimeno, B. Parvais, N. Planes, M. Haond, J.-P. Raskin, D. Flandre
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 128-131
DOI: 10.1109/ULIS.2017.7962581

Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements

Author(s): B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, J.-P. Raskin
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 228-230
DOI: 10.1109/ULIS.2017.7962569

Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

Author(s): A. Idrissi-El Oudrhiri, S. Martinie, J-C. Barbe, O. Rozeau, C. Le Royer, M-A. Jaud, J. Lacord, N. Bernier, L. Grenouillet, P. Rivallin, J. Pelloux-Prayer, M. Casse, M. Mouis
Published in: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Page(s) 206-209
DOI: 10.1109/SISPAD.2015.7292295

Scatterometry control for multiple electron beam lithography

Author(s): Yoann Blancquaert, Nivea Figueiro, Thibault Labbaye, Francisco Sanchez, Stephane Heraud, Roy Koret, Matthew Sendelbach, Ralf Michel, Shay Wolfling, Stephane Rey, Laurent Pain
Published in: Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, Page(s) 101451F
DOI: 10.1117/12.2261389

Smart solutions for efficient dual strain integration for future FDSOI generations

Author(s): A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, N. Rambal, J.-P. Pedini, S. Kerdiles, P. Besson, J.-M. Hartmann, D. Marseilhan, B. Mathieu, R. Berthelon, M. Casse, F. Andrieu, D. Rouchon, O. Weber, F. Boeuf, M. Haond, A. Claverie, M. Vinet
Published in: 2016 IEEE Symposium on VLSI Technology, 2016, Page(s) 1-2
DOI: 10.1109/VLSIT.2016.7573406

Field mapping of semiconductor devices in a transmission electron microscope with nanometre scale resolution by off-axis electron holography and precession electron diffraction

Author(s): David Cooper, Nicolas Bernier, Jean-Luc Rouviere
Published in: 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 2015, Page(s) 777-780
DOI: 10.1109/NANO.2015.7388725

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Author(s): S. Barraud, V. Lapras, M.P. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Posseme, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet
Published in: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 17.6.1-17.6.4
DOI: 10.1109/IEDM.2016.7838441

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration

Author(s): R. Berthelon, F. Andrieu, P. Perreau, E. Baylac, A. Pofelski, E. Josse, D. Dutartre, A. Claverie, M. Haond
Published in: 2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, Page(s) 127-130
DOI: 10.1109/ESSDERC.2016.7599604

Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs

Author(s): R. Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, E. Serret, A. Aurand, S. Delmedico, V. Farys, C. Bernicot, E. Bechet, E. Bernard, T. Poiroux, D. Rideau, P. Scheer, E. Baylac, P. Perreau, M.A. Jaud, J. Lacord, E. Petitprez, A. Pofelski, S. Ortolland, P. Sardin, D. Dutartre, A. Claverie, M. Vinet, J.C. Marin, M. Haond
Published in: 2016 IEEE Symposium on VLSI Technology, 2016, Page(s) 1-2
DOI: 10.1109/VLSIT.2016.7573425

A novel dual isolation scheme for stress and back-bias maximum efficiency in FDSOI Technology

Author(s): R. Berthelon, F. Andrieu, P. Perreau, D. Cooper, F. Roze, O. Gourhant, P. Rivallin, N. Bernier, A. Cros, C. Ndiaye, E. Baylac, E. Souchier, D. Dutartre, A. Claverie, O. Weber, E. Josse, M. Vinet, M. Haond
Published in: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 17.7.1-17.7.4
DOI: 10.1109/IEDM.2016.7838442

Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

Author(s): R. Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, E. Baylac, D. Dutartre, E. Josse, A. Claverie, M. Haond
Published in: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 88-91
DOI: 10.1109/ULIS.2016.7440059

Mechanical simulations of BOX creep for strained FDSOI

Author(s): R. Berthelon, F. Andrieu, B. Mathieu, D. Dutartre, C. Le Royer, M. Vinet, A. Claverie
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 91-94
DOI: 10.1109/ULIS.2017.7962609

Impact of strain on access resistance in planar and nanowire CMOS devices

Author(s): R. Berthelon, F. Andneu, F. Triozon, M. Casse, L. Bourdet, G. Ghibaudo, D. Rideau, Y. M. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet
Published in: 2017 Symposium on VLSI Technology, 2017, Page(s) T224-T225
DOI: 10.23919/VLSIT.2017.7998180

Physical transport simulation for path-finding and device optimization

Author(s): M. Karner, Z. Stanojevic, O. Baumgartner, HW. Karner, C. Kernstock, H. Demel, F. Mitterbauer
Published in: 2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016, Page(s) 208-209
DOI: 10.1109/SNW.2016.7578054

Phase-space solution of the subband Boltzmann transport equation for nano-scale TCAD

Author(s): Z. Stanojevic, M. Karner, O. Baumgartner, H. W. Karner, C. Kernstock, H. Demel, F. Mitterbauer
Published in: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Page(s) 65-67
DOI: 10.1109/SISPAD.2016.7605149

Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations

Author(s): M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. W. Karner, G. Rzepa, T. Grasset
Published in: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 30.7.1-30.7.4
DOI: 10.1109/IEDM.2016.7838516

Towards physics-based DTCO for performance of advanced technology nodes

Author(s): Z. Stanojevic, O. Baumgartner, M. Karner, C. Kernstock, H. W. Karner, H. Demel, G. Strof, F. Mitterbauer
Published in: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Page(s) 245-248
DOI: 10.23919/SISPAD.2017.8085310

TCAD-based characterization of logic cells: Power, performance, area, and variability

Author(s): HW. Karner, C. Kernstock, Z. Stanojevic, O. Baumgartner, F. Schanovsky, M. Karner, D. Helms, R. Eilers, M. Metzdorf
Published in: 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, Page(s) 1-2
DOI: 10.1109/VLSI-TSA.2017.7942453

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Author(s): R. Carter, J. Mazurier, L. Pirro, J-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P-Y. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub
Published in: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 2.2.1-2.2.4
DOI: 10.1109/IEDM.2016.7838029

Out-of-equilibrium body potential measurements in pseudo-MOSFET for biosensing

Author(s): Licinius Benea, Maryline Bawedin, Cecile Delacour, Sorin Cristoloveanu, Irina Ionica
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 19-22
DOI: 10.1109/ULIS.2017.7962590

BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization

Author(s): F. Cacho, A. Cros, X. Federspiel, V. Huard, C. Roma
Published in: 2016 IEEE International Reliability Physics Symposium (IRPS), 2016, Page(s) 7C-1-1-7C-1-6
DOI: 10.1109/IRPS.2016.7574581

Localized STRASS Technique on Advanced FDSOI Platform: Highly Tensile Si Demonstration for Dual Strain CMOS Integration

Author(s): A. Bonnevialle, S. Reboh, C. Le Royer, Y. Morand, J.-M. Hartmann, D. Rouchon, J.-M. Pedini, C. Tabone, N. Rambal, A. Payet, C. Plantier, F. Boeuf, M. Haond, A. Claverie, M. Vinet
Published in: 2016

A New Method to Induce Local Tensile Strain in SOI Wafers: First Strain Results of the “BOX Creep” Technique”

Author(s): A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, J.-M. Pédini, A. Roule, D. Marseilhan, P. Besson, D. Rouchon, N. Bernier, C. Tabone, C. Plantier, M. Vinet,
Published in: 2015

Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm channel pitch and opportunities for stacked-Nanowires architectures

Author(s): L. Gaben, S. Barraud, P. Pimenta-Barros, Y. Morand, J. Pradelles, M.-P. Samson, B. Previtali, P. Besson, F. Allain, S. Monfray, F. Boeuf, T. Skotnicki, F. Balestra3 and M. Vine
Published in: 2015

Fast and Accurate solution of inverse problem for in-line monitoring of strain field determined by High Resolution X-Ray Diffraction Reciprocal Space Mapping

Author(s): A DURAND, M KAUFLING, D LE-CUNFF, D ROUCHON, P GERGAUD 
Published in: 2016

Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

Author(s): F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. Ayres de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi, D. Fried, P. Morin, J.P. Noel, B. Giraud, S. Thuries, F. Arnaud, M. Vinet
Published in: 2017

“Material and Device Innovation for Cost Effective CMOS Scaling Beyond 28nm”

Author(s): W. Schwarzenbach, F. Allibert, C. Figuet, C. Girard and C. Maleville
Published in: 2016

“Beyond Silicon CMOS: Progress and challenges”

Author(s): B.-Y. Nguyen, M.Sadaka, G.Gaudin, W. Schwarzenbach, K.Boudelle,C.Figuet and C.Maleville
Published in: 2016

“Investigation of Hot Carrier reliability of SOI and sSOI transistors using Back Bias”

Author(s): G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu and C. Mazure
Published in: 2015

“P-FET Co-Integration on Si and Strained SiGe Dual Channel Substrates Obtained by Ge Local Enrichment Technique”

Author(s): Nguyen, S. Barraud, L. Hutin, C. Tabone, F. Glowacki, J.-M. Hartmann, M.-P. Samson†, L. Ecarnot, B.-Y. Nguyen¤, C. Maleville, C. Mazuré, O. Faynot, M. Vinet
Published in: 2015

“High Mobility Materials on Insulator for Advanced Technology Nodes”

Author(s): J. Widieza, F. Mazena, J-M. Hartmanna, Y. Bogumilowicza, E. Augendrea, C. Veytizoub, S. Solliera, M. Martinc, M-C. Rourea, V. Loupa, C. Euvrada, A. Seignarda, T. Baronc, R. Ciproc, F. Bassanic, A-M. Papona, C. Guedja, I. Huyetb, M. Rivoirea, P. Bessona, C. Figuetb, W. Schwarzenbachb, D. Delpratb and T. Signamarcheixa
Published in: 2015

“Designing with FD-SOI“ & “Interconnected World”.

Author(s): J. Kunkel
Published in: 2015

“Substrate maturity+D61:M61+D61:M61 and readiness in large volume to support mass adoption of ULP FDSOI platforms”

Author(s): C.Maleville
Published in: 2016

“Designing with FD-SOI Technologies”




“How innovation and eco-system in Europe can enable future requirements in automotive electronics”

Author(s): N. Kernevez
Published in: 2015

“Engineered substrates for low-power devices”

Author(s): T. Piliszczuk
Published in: 2015

“Novel chip embedding and interconnection technology for mm-wave System-in-Package (SiP) applications,”

Author(s): C. Landesberger et al.
Published in: 2018

“Slow-wave coplanar strip line based Low-power 80-GHz Voltage Control Oscillator on 22-nm FDSOI technology,”

Author(s): T. Lim et al.
Published in: 2017

Investigation of hot carrier reliability of SOI and strained SOI transistors using back bias

Author(s): G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu, C. Mazure
Published in: 2015 International Symposium on VLSI Technology, Systems and Applications, 2015, Page(s) 1-2
DOI: 10.1109/VLSI-TSA.2015.7117577

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

Author(s): G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu
Published in: 2015 IEEE International Reliability Physics Symposium, 2015, Page(s) 2F.1.1-2F.1.5
DOI: 10.1109/IRPS.2015.7112691

Systematic evaluation of SOI Buried Oxide reliability for partially depleted and fully depleted applications

Author(s): W. Schwarzenbach, C. Malaquin, F. Allibert, G. Besnard, B.-Y. Nguyen
Published in: 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, Page(s) 1-3
DOI: 10.1109/S3S.2015.7333496

Analysis and modelling of temperature effect on DIBL in UTBB FD SOI MOSFETs

Author(s): A. S. N. Pereira, G. de Streel, N. Planes, M. Haond, R. Giacomini, D. Flandre, V. Kilchytska
Published in: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 116-119
DOI: 10.1109/ULIS.2016.7440066

Threshold voltage and on-current Variability related to interface traps spatial distribution

Author(s): V. Velayudhan, J. Martin-Martinez, M. Porti, C. Couso, R. Rodriguez, M. Nafria, X. Aymerich, C. Marquez, F. Gamiz
Published in: 2015 45th European Solid State Device Research Conference (ESSDERC), 2015, Page(s) 230-233
DOI: 10.1109/ESSDERC.2015.7324756

Electrical characterization of Random Telegraph Noise in back-biased Ultrathin Silicon-On-Insulator MOSFETs

Author(s): Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata
Published in: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 40-43
DOI: 10.1109/ULIS.2016.7440047

Impact of S/D tunneling in ultrascaled devices, a Multi-Subband Ensemble Monte Carlo study

Author(s): C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
Published in: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Page(s) 214-217
DOI: 10.1109/SISPAD.2015.7292297

Multi-Subband Ensemble Monte Carlo simulation of Si nanowire MOSFETs

Author(s): Luca Donetti, Carlos Sampedro, Francisco Gamiz, Andres Godoy, Francisco J. Garcia-Ruiz, Ewan Towiez, Vihar P. Georgiev, Salvatore Maria Amoroso, Craig Riddet, Asen Asenov
Published in: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Page(s) 353-356
DOI: 10.1109/SISPAD.2015.7292332

Confinement orientation effects in S/D tunneling

Author(s): C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
Published in: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 100-103
DOI: 10.1109/ULIS.2016.7440062

Physical modeling - A new paradigm in device simulation

Author(s): Z. Stanojevic, O. Baumgartner, F. Mitterbauer, H. Demel, C. Kernstock, M. Karner, V. Eyert, A. France-Lanord, P. Saxe, C. Freeman, E. Wimmer
Published in: 2015 IEEE International Electron Devices Meeting (IEDM), 2015, Page(s) 5.1.1-5.1.4
DOI: 10.1109/IEDM.2015.7409631

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

Author(s): D. Benoit, J. Mazurier, B. Varadarajan, S. Chhun, S. Lagrasta, C. Gaumer, D. Galpin, C. Fenouillet-Beranger, D. Vo-Thanh, D. Barge, R. Duru, R. Beneyton, B. Gong, N. Sun, N. Chauvet, P. Ruault, D. Winandy, B. van Schravendijk, P. Meijer, O. Hinsinger
Published in: 2015 IEEE International Electron Devices Meeting (IEDM), 2015, Page(s) 8.6.1-8.6.4
DOI: 10.1109/IEDM.2015.7409656

Designing wit FD-SOI technologies

Author(s): C.Maleville
Published in: 2017

Advanced CMOS Nodes (FDSOI, FinFET) usage for High Reliability Markets from Device and Design

Author(s): P.Gupta
Published in: 2016

Engineered substrates for Moore and more than Moore's law: Device scaling: Entering the substrate era

Author(s): Christophe Maleville
Published in: 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, Page(s) 1-5
DOI: 10.1109/S3S.2015.7333494

Low-variation SRAM bitcells in 22nm FDSOI technology

Author(s): V. Joshi, H. Ramamurthy, S. Balasubramanian, S. Seo, H. Yoon, X. Zou, N. Chan, J. Yun, T. Klick, E. Smith, J. Schmid, R. vanBentum, J. Faul, C. Weintraub
Published in: 2017 Symposium on VLSI Technology, 2017, Page(s) T222-T223
DOI: 10.23919/VLSIT.2017.7998179

The FDSOI history and its future

Author(s): P.Flatresse
Published in: 2017

Keynote - The FDSOI saga

Author(s): C.Mazure
Published in: 2017

SU3200 use case to enable Angström level FDSOI uniformity all wafers all points

Author(s): N.Daval
Published in: 2017

Low latency digital regenerator for dual polarization QAM signals

Author(s): Fred Buchali, Laurent Schmalen, Qian Hu, Di Che
Published in: 2015 European Conference on Optical Communication (ECOC), 2015, Page(s) 1-3
DOI: 10.1109/ECOC.2015.7341622

Preemphased Prime Frequency Multicarrier Bases ENOB Assessment and its Application for Optimizing a Dual-Carrier 1-Tb/s QAM Transmitter

Author(s): F.Buchali
Published in: 2016

Low-power inductorless RF receiver front-end with IIP2 calibration through body bias control in 28nm UTBB FDSOI

Author(s): Dajana Danilovic, Vladimir Milovanovic, Andreia Cathelin, Andrei Vladimirescu, Borivoje Nikolic
Published in: 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016, Page(s) 87-90
DOI: 10.1109/RFIC.2016.7508257

A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI

Author(s): Ilias Sourikopoulos, Antoine Frappe, Andreia Cathelin, Laurent Clavier, Andreas Kaiser
Published in: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, Page(s) 145-148
DOI: 10.1109/ESSCIRC.2016.7598263

A 0.0175mm 2 600µW 32kHz input 307MHz output PLL with 190ps<inf>rms</inf> jitter in 28nm FD-SOI

Author(s): Abhirup Lahiri, Nitin Gupta
Published in: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, Page(s) 339-342
DOI: 10.1109/ESSCIRC.2016.7598311

A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers

Author(s): Reda Kasri, Eric Klumperink, Philippe Cathelin, Eric Toumier, Bram Nauta
Published in: 2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, Page(s) 1-4
DOI: 10.1109/CICC.2017.7993644

RF/analog and mixed-signal design techniques in FD-SOI technology

Author(s): Andreia Cathelin
Published in: 2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, Page(s) 1-53
DOI: 10.1109/CICC.2017.7993721

Class AB Base-Band Amplifier Design with Body Biasing in 28nm UTBB FD-SOI CMOS

Author(s): Mirjana Videnovic-Misic
Published in: 2017

“High Sigma Functional Qualification for Flipflops using MunEDA WiCkeD,”

Author(s): N. Ben Salem, R.K. Gupta
Published in: 2017

Catalytic ALD of SiO2 as spacer for an E-Beam direct write self-aligned double patterning process on 300 mm wafers

Author(s): K. Kühnel, S. Riedel, W. Weinreich, X. Thrun, M. Czernohorsky, B. Pätzold, M. Rudolph
Published in: 2016

Oxidation of Germanium at Low-temperature by Plasma Enhanced Processing

Author(s): W. Lerch, N. Sacher, W. Kegel, J. Niess, M. Czernohorsky
Published in: 2016

Cobalt MOCVD as a Flexible Process in Semiconductor Industry

Author(s): L. Gerlich, M. Wislicenus, B. Uhlig, S. Riedel, R. Liske
Published in: 2016

Selective Area Deposition of MOCVD Co for BEOL Capping Applications

Author(s): M. Wislicenus, T. Martin, L. Gerlich, B. Uhlig
Published in: 2016

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

Author(s): A.S.N. Pereira, G. de Streel, N. Planes, M. Haond, R. Giacomini, D. Flandre, V. Kilchytska
Published in: Solid-State Electronics, Issue 128, 2017, Page(s) 67-71, ISSN 0038-1101
DOI: 10.1016/j.sse.2016.10.017

High-K metal gate stacks with ultra-thin interfacial layers formed by low temperature microwave-based plasma oxidation

Author(s): M. Czernohorsky, K. Seidel, K. Kühnel, J. Niess, N. Sacher, W. Kegel, W. Lerch
Published in: Microelectronic Engineering, Issue 178, 2017, Page(s) 262-265, ISSN 0167-9317
DOI: 10.1016/j.mee.2017.05.041

In-line monitoring of strain distribution using high resolution X-ray Reciprocal space mapping into 20 nm SiGe pMOS

Author(s): Aurèle Durand, Melissa Kaufling, Delphine Le-Cunff, Denis Rouchon, Patrice Gergaud
Published in: Materials Science in Semiconductor Processing, Issue 70, 2017, Page(s) 99-104, ISSN 1369-8001
DOI: 10.1016/j.mssp.2016.12.003

Benefits of XPS nanocharacterization for process development and industrial control of thin SiGe channel layers in advanced CMOS technologies

Author(s): L. Fauquier, B. Pelissier, D. Jalabert, F. Pierre, J.M. Hartmann, F. Rozé, D. Doloy, D. Le Cunff, C. Beitia, T. Baron
Published in: Materials Science in Semiconductor Processing, Issue 70, 2017, Page(s) 105-110, ISSN 1369-8001
DOI: 10.1016/j.mssp.2016.10.028

Strain mapping of semiconductor specimens with nm-scale resolution in a transmission electron microscope

Author(s): David Cooper, Thibaud Denneulin, Nicolas Bernier, Armand Béché, Jean-Luc Rouvière
Published in: Micron, Issue 80, 2016, Page(s) 145-165, ISSN 0968-4328
DOI: 10.1016/j.micron.2015.09.001

Using Electron Diffraction Techniques, CBED and N-PED to measure Strain with High Precision and High Spatial Resolution

Author(s): J.L. Rouviere, Y. Martin, N. Bernier, M. Vigouroux, D. Cooper, J.M. Zuo
Published in: Microscopy and Microanalysis, Issue 21/S3, 2015, Page(s) 2209-2210, ISSN 1431-9276
DOI: 10.1017/S1431927615011824

Nanoscale Strain Mapping in Embedded SiGe Devices by Dual Lens Dark Field Electron Holography and Precession Electron Diffraction

Author(s): Y. Y. Wang, D. Cooper, J. Rouviere, C.E. Murray, N. Bernier, J. Bruley
Published in: Microscopy and Microanalysis, Issue 21/S3, 2015, Page(s) 1963-1964, ISSN 1431-9276
DOI: 10.1017/S1431927615010594

Combining 2 nm Spatial Resolution and 0.02% Precision for Deformation Mapping of Semiconductor Specimens in a Transmission Electron Microscope by Precession Electron Diffraction

Author(s): David Cooper, Nicolas Bernier, Jean-Luc Rouvière
Published in: Nano Letters, Issue 15/8, 2015, Page(s) 5289-5294, ISSN 1530-6984
DOI: 10.1021/acs.nanolett.5b01614

Strain mapping at the nanoscale using precession electron diffraction in transmission electron microscope with off axis camera

Author(s): M. P. Vigouroux, V. Delaye, N. Bernier, R. Cipro, D. Lafond, G. Audoit, T. Baron, J. L. Rouvière, M. Martin, B. Chenevier, F. Bertin
Published in: Applied Physics Letters, Issue 105/19, 2014, Page(s) 191906, ISSN 0003-6951
DOI: 10.1063/1.4901435

Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14nm UTBB FDSOI technology

Author(s): R. Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, E. Baylac, D. Dutartre, E. Josse, A. Claverie, M. Haond
Published in: Solid-State Electronics, Issue 128, 2017, Page(s) 72-79, ISSN 0038-1101
DOI: 10.1016/j.sse.2016.10.011

Implementation of Band-to-Band Tunneling Phenomena in a Multisubband Ensemble Monte Carlo Simulator: Application to Silicon TFETs

Author(s): Cristina Medina-Bailon, Jose L. Padilla, Carlos Sampedro, Cem Alper, Francisco Gamiz, Adrian Mihai Ionescu
Published in: IEEE Transactions on Electron Devices, Issue 64/8, 2017, Page(s) 3084-3091, ISSN 0018-9383
DOI: 10.1109/TED.2017.2715403

Insights on the Body Charging and Noise Generation by Impact Ionization in Fully Depleted SOI MOSFETs

Author(s): Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata
Published in: IEEE Transactions on Electron Devices, Issue 64/12, 2017, Page(s) 5093-5098, ISSN 0018-9383
DOI: 10.1109/TED.2017.2762733

Systematic method for electrical characterization of random telegraph noise in MOSFETs

Author(s): Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata
Published in: Solid-State Electronics, Issue 128, 2017, Page(s) 115-120, ISSN 0038-1101
DOI: 10.1016/j.sse.2016.10.031

The Measurement of Strain, Chemistry and Electric Fields by STEM based Techniques

Author(s): J.-L. Rouviere, B. Haas, E. Robin, D. Cooper, N. Bernier, M. Williamson
Published in: Microscopy and Microanalysis, Issue 23/S1, 2017, Page(s) 1414-1415, ISSN 1431-9276
DOI: 10.1017/S1431927617007735

300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut  Technology

Author(s): J. Widiez, C. Veytizou, J.-M. Hartmann, V. Loup, P. Besson, N. Baumel, C. Figuet, I. Huyet, F. Mazen, W. Schwarzenbach, C. Tempesta, L. Ecarnot
Published in: ECS Transactions, Issue 75/8, 2016, Page(s) 79-88, ISSN 1938-5862
DOI: 10.1149/07508.0079ecst

Out-of-equilibrium body potential measurements in pseudo-MOSFET for sensing applications

Author(s): Licinius Benea, Maryline Bawedin, Cécile Delacour, Irina Ionica
Published in: Solid-State Electronics, 2017, ISSN 0038-1101
DOI: 10.1016/j.sse.2017.11.010

(Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers

Author(s): G. Kozlowski, O. Fursenko, P. Zaumseil, T. Schroeder, M. Vorderwestner, P. Storck
Published in: ECS Transactions, Issue 50/9, 2013, Page(s) 613-621, ISSN 1938-5862
DOI: 10.1149/05009.0613ecst

Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

Author(s): Walter Schwarzenbach, Bich-Yen Nguyen, Frederic Allibert, Christophe Girard, Christophe Maleville
Published in: Solid-State Electronics, Issue 117, 2016, Page(s) 2-9, ISSN 0038-1101
DOI: 10.1016/j.sse.2015.11.008

(Invited) Low-Temperature Microwave-Based Plasma Oxidation of Ge and Oxidation of Silicon Followed by Plasma Nitridation

Author(s): W. Lerch, T. Schick, N. Sacher, W. Kegel, J. Niess, M. Czernohorsky, S. Riedel
Published in: ECS Transactions, Issue 72/4, 2016, Page(s) 101-114, ISSN 1938-5862
DOI: 10.1149/07204.0101ecst

Impact of non uniform strain configuration on transport properties for FD14+ devices

Author(s): C. Medina-Bailon, C. Sampedro, F. Gámiz, A. Godoy, L. Donetti
Published in: Solid-State Electronics, Issue 115, 2016, Page(s) 232-236, ISSN 0038-1101
DOI: 10.1016/j.sse.2015.08.013

Direct Characterization of Impact Ionization Current in Silicon-on-Insulator Body-Contacted MOSFETs

Author(s): C. Marquez, N. Rodriguez, J. M. Montes, R. Ruiz, F. Gamiz, C. Sampedro, A. Ohata
Published in: ECS Transactions, Issue 66/5, 2015, Page(s) 93-99, ISSN 1938-5862
DOI: 10.1149/06605.0093ecst

Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation

Author(s): Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Rafael Ruiz, Akiko Ohata
Published in: Solid-State Electronics, Issue 117, 2016, Page(s) 60-65, ISSN 0038-1101
DOI: 10.1016/j.sse.2015.11.022

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping

Author(s): Guerric de Streel, Francois Stas, Thibaut Gurne, Francois Durant, Charlotte Frenkel, Andreia Cathelin, David Bol
Published in: IEEE Journal of Solid-State Circuits, Issue 52/4, 2017, Page(s) 1163-1177, ISSN 0018-9200
DOI: 10.1109/JSSC.2016.2645607

Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

Author(s): Andreia Cathelin
Published in: IEEE Solid-State Circuits Magazine, Issue 9/4, 2017, Page(s) 18-26, ISSN 1943-0582
DOI: 10.1109/MSSC.2017.2745738

All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs

Author(s): Theano A. Karatsori, Christoforos G. Theodorou, Emmanuel Josse, Charalabos A. Dimitriadis, G. Ghibaudo
Published in: IEEE Transactions on Electron Devices, Issue 64/5, 2017, Page(s) 2080-2085, ISSN 0018-9383
DOI: 10.1109/TED.2017.2686381

Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

Author(s): Theano A. Karatsori, Christoforos G. Theodorou, Xavier Mescot, Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, Charalabos A. Dimitriadis
Published in: IEEE Transactions on Electron Devices, 2016, Page(s) 1-7, ISSN 0018-9383
DOI: 10.1109/TED.2016.2583504

Characterization and industrial control of local stress in microelectronics: - Applications to advanced transistors technology of 20 nm

Author(s): A.Durand
Published in: 2016