Synthesis and Performance Optimization of a Switching Nano-crossbar Computer

Informations projet

NANOxCOMP

N° de convention de subvention: 691178

DOI

10.3030/691178

Projet clôturé

Date de signature de la CE 5 Octobre 2015

Date de début 1 Decembre 2015

Date de fin 30 Novembre 2019

Financé au titre de

• EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions

Coût total

€ 577 035,00

Contribution de l’UE

€ 577 035,00

Coordonné par

ISTANBUL TEKNIK UNIVERSITESI
Türkiye

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Other (2)

Synthesis tool

Deliverable 1.1 - Software: A software tool synthesizing arrays with optimal sizes.

Performance optimization tool

Deliverable 2.1 - Software: A software tool having inputs of “defect rates”, “target Boolean functions”, and “required accuracy”, and an output of “crossbar size”.

Documents, reports (6)

Conference paper-2

Deliverable 4.1 - Publication: A paper submitted to a leading conference on computer-aided design (CAD) of digital circuits such as DAC, ASP-DAC, DATE, DDECS, NANOARCH, etc.

Patent and/or Journal paper-2

Deliverable 5.2 - Publication: A European patent filed and/or a paper submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Conference paper-1

Deliverable 1.2 - Publication: A paper submitted to a leading conference on computer-aided design (CAD) of digital circuits such as DAC, ASP-DAC, DATE, DDECS, NANOARCH, etc.

Journal papers

Deliverable 2.2 - Publication: At least two papers submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Report and/or Article

Deliverable 5.1 - Report/Article: A report/article on future directions of nano-crossbar based computing architectures is publicly released with lessons learned in this project.

Patent and/or Journal paper-1

Deliverable 4.2 - Publication: A European patent filed or a paper submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Publications

Peer reviewed articles (10)

Logic synthesis and testing techniques for switching nano-crossbar arrays

Auteurs: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
Publié dans: Microprocessors and Microsystems, Numéro 54, 2017, Page(s) 14-25, ISSN 0141-9331
Éditeur: Elsevier BV
DOI: 10.1016/j.micpro.2017.08.004

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
Publié dans: Microprocessors and Microsystems, Numéro 56, 2018, Page(s) 193-203, ISSN 0141-9331
Éditeur: Elsevier BV
DOI: 10.1016/j.micpro.2017.12.003

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

Auteurs: Onur Tunali, Mustafa Altun
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numéro 36-5, 2017, Page(s) 1-1, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2016.2602804

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Auteurs: Levent Aksoy, Mustafa Altun
Publié dans: IEEE Transactions on Computers, Numéro 69-3, 2019, Page(s) 1-1, ISSN 0018-9340
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2019.2950663

Composition of switching lattices for regular and for decomposed functions

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Publié dans: Microprocessors and Microsystems, Numéro 60, 2018, Page(s) 207-218, ISSN 0141-9331
Éditeur: Elsevier BV
DOI: 10.1016/j.micpro.2018.05.004

Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

Auteurs: M. Ceylan Morgül, Mustafa Altun
Publié dans: Integration, Numéro 64, 2019, Page(s) 60-70, ISSN 0167-9260
Éditeur: Elsevier BV
DOI: 10.1016/j.vlsi.2018.08.002

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Auteurs: Onur Tunali, M. Ceylan Morgul, Mustafa Altun
Publié dans: IEEE Micro, Numéro 38/5, 2018, Page(s) 22-31, ISSN 0272-1732
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2018.053631138

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Auteurs: Furkan Peker, Mustafa Altun
Publié dans: IEEE Transactions on Multi-Scale Computing Systems, Numéro 4/4, 2018, Page(s) 522-532, ISSN 2332-7766
Éditeur: IEEE
DOI: 10.1109/tmscs.2018.2829518

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

Auteurs: Onur Tunali, Mustafa Altun
Publié dans: ACM Computing Surveys, Numéro 50/6, 2018, Page(s) 1-35, ISSN 0360-0300
Éditeur: Association for Computing Machinary, Inc.
DOI: 10.1145/3125641

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Auteurs: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz
Publié dans: Microelectronics Journal, Numéro 89, 2019, Page(s) 30-36, ISSN 0026-2692
Éditeur: Mackintosh Publications
DOI: 10.1016/j.mejo.2019.05.008

Conference proceedings (17)

Computing with nano-crossbar arrays: Logic synthesis and fault tolerance

Auteurs: Mustafa Altun, Valentina Ciriani, Mehdi Tahoori
Publié dans: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Page(s) 278-281, ISBN 978-3-9815370-8-6
Éditeur: IEEE
DOI: 10.23919/DATE.2017.7926998

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Publié dans: 2017 Euromicro Conference on Digital System Design (DSD), 2017, Page(s) 137-144, ISBN 978-1-5386-2146-2
Éditeur: IEEE
DOI: 10.1109/DSD.2017.54

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
Publié dans: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Page(s) 423-430, ISBN 978-1-5090-2817-7
Éditeur: IEEE
DOI: 10.1109/DSD.2016.75

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer

Auteurs: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
Publié dans: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Page(s) 334-341, ISBN 978-1-5090-2817-7
Éditeur: IEEE
DOI: 10.1109/DSD.2016.45

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

Auteurs: Muhammed Ceylan Morgul, Furkan Peker, Mustafa Altun
Publié dans: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, Page(s) 437-442, ISBN 978-1-4673-9039-2
Éditeur: IEEE
DOI: 10.1109/ISVLSI.2016.100

Synthesis on switching lattices of Dimension-reducible Boolean functions

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Publié dans: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Page(s) 1-6, ISBN 978-1-5090-3561-8
Éditeur: IEEE
DOI: 10.1109/VLSI-SoC.2016.7753577

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Auteurs: Serzat Safaltin, Oguz Gencer, M. Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, Mustafa Altun
Publié dans: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 504-509, ISBN 978-3-9819263-2-3
Éditeur: IEEE
DOI: 10.23919/date.2019.8715123

Integrated Synthesis Methodology for Crossbar Arrays

Auteurs: M. Ceylan Morgul, Dan Alexandrescu, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, E. Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan
Publié dans: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '18, 2018, Page(s) 91-97, ISBN 9781-450358156
Éditeur: ACM Press
DOI: 10.1145/3232195.3232211

Noise-induced Performance Enhancement of Variability-aware Memristor Networks

Auteurs: Vasileios Ntinas, Iosif-Angelos Fyrigos, Georgios Ch. Sirakoulis, Antonio Rubio, Javier Martin-Martinez, Rosana Rodriguez, Montserrat Nafria
Publié dans: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Page(s) 731-734, ISBN 978-1-7281-0996-1
Éditeur: IEEE
DOI: 10.1109/ICECS46596.2019.8965134

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Auteurs: Levent Aksoy, Mustafa Altun
Publié dans: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 1637-1642, ISBN 978-3-9819263-2-3
Éditeur: IEEE
DOI: 10.23919/date.2019.8714809

Analog Neural Network based on Memristor Crossbar Arrays

Auteurs: Hacer A. Yildiz, Mustafa Altun, Ali Dogus Gungordu, Mircea R. Stan
Publié dans: 2019 11th International Conference on Electrical and Electronics Engineering (ELECO), 2019, Page(s) 358-361, ISBN 978-605-01-1275-7
Éditeur: IEEE
DOI: 10.23919/eleco47770.2019.8990597

Testability of Switching Lattices in the Cellular Fault Model

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini
Publié dans: 2019 22nd Euromicro Conference on Digital System Design (DSD), 2019, Page(s) 320-327, ISBN 978-1-7281-2862-7
Éditeur: IEEE
DOI: 10.1109/dsd.2019.00054

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Auteurs: Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Ioana Vatajelu
Publié dans: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6, ISBN 978-1-7281-1756-0
Éditeur: IEEE
DOI: 10.1109/latw.2019.8704615

Testability of Switching Lattices in the Stuck at Fault Model

Auteurs: Anna Bernasconi, Valentina Ciriani, Luca Frontini
Publié dans: 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, Page(s) 213-218, ISBN 978-1-5386-4756-1
Éditeur: IEEE
DOI: 10.1109/vlsi-soc.2018.8644806

Logic synthesis and defect tolerance for memristive crossbar arrays

Auteurs: Onur Tunali, Mustafa Altun
Publié dans: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 425-430, ISBN 978-3-9819263-0-9
Éditeur: IEEE
DOI: 10.23919/date.2018.8342047

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

Auteurs: Onur Tunali, Mustafa Altun
Publié dans: 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017, Page(s) 534-537, ISBN 978-1-5386-1911-7
Éditeur: IEEE
DOI: 10.1109/icecs.2017.8292053

Spin-torque memristor based offset cancellation technique for sense amplifiers

Auteurs: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, Kaushik Roy
Publié dans: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, Page(s) 1-4, ISBN 978-1-5090-5052-9
Éditeur: IEEE
DOI: 10.1109/smacd.2017.7981595

Book chapters (1)

Computing with Emerging Nanotechnologies

Auteurs: M. Altun
Publié dans: Low-Dimensional and Nanostructured Materials and Devices, 2016, Page(s) 635-660, ISBN 978-3-319-25340-4
Éditeur: Springer International Publishing
DOI: 10.1007/978-3-319-25340-4_26