Skip to main content

Synthesis and Performance Optimization of a Switching Nano-crossbar Computer

Deliverables

Synthesis tool

Deliverable 1.1 - Software: A software tool synthesizing arrays with optimal sizes.

Performance optimization tool

Deliverable 2.1 - Software: A software tool having inputs of “defect rates”, “target Boolean functions”, and “required accuracy”, and an output of “crossbar size”.

Conference paper-2

Deliverable 4.1 - Publication: A paper submitted to a leading conference on computer-aided design (CAD) of digital circuits such as DAC, ASP-DAC, DATE, DDECS, NANOARCH, etc.

Patent and/or Journal paper-2

Deliverable 5.2 - Publication: A European patent filed and/or a paper submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Conference paper-1

Deliverable 1.2 - Publication: A paper submitted to a leading conference on computer-aided design (CAD) of digital circuits such as DAC, ASP-DAC, DATE, DDECS, NANOARCH, etc.

Journal papers

Deliverable 2.2 - Publication: At least two papers submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Report and/or Article

Deliverable 5.1 - Report/Article: A report/article on future directions of nano-crossbar based computing architectures is publicly released with lessons learned in this project.

Patent and/or Journal paper-1

Deliverable 4.2 - Publication: A European patent filed or a paper submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Searching for OpenAIRE data...

Publications

Logic synthesis and testing techniques for switching nano-crossbar arrays

Author(s): Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
Published in: Microprocessors and Microsystems, Issue 54, 2017, Page(s) 14-25, ISSN 0141-9331
DOI: 10.1016/j.micpro.2017.08.004

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
Published in: Microprocessors and Microsystems, Issue 56, 2018, Page(s) 193-203, ISSN 0141-9331
DOI: 10.1016/j.micpro.2017.12.003

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

Author(s): Onur Tunali, Mustafa Altun
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Issue 36-5, 2017, Page(s) 1-1, ISSN 0278-0070
DOI: 10.1109/TCAD.2016.2602804

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Author(s): Levent Aksoy, Mustafa Altun
Published in: IEEE Transactions on Computers, Issue 69-3, 2019, Page(s) 1-1, ISSN 0018-9340
DOI: 10.1109/tc.2019.2950663

Composition of switching lattices for regular and for decomposed functions

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Published in: Microprocessors and Microsystems, Issue 60, 2018, Page(s) 207-218, ISSN 0141-9331
DOI: 10.1016/j.micpro.2018.05.004

Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

Author(s): M. Ceylan Morgül, Mustafa Altun
Published in: Integration, Issue 64, 2019, Page(s) 60-70, ISSN 0167-9260
DOI: 10.1016/j.vlsi.2018.08.002

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Author(s): Onur Tunali, M. Ceylan Morgul, Mustafa Altun
Published in: IEEE Micro, Issue 38/5, 2018, Page(s) 22-31, ISSN 0272-1732
DOI: 10.1109/mm.2018.053631138

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Author(s): Furkan Peker, Mustafa Altun
Published in: IEEE Transactions on Multi-Scale Computing Systems, Issue 4/4, 2018, Page(s) 522-532, ISSN 2332-7766
DOI: 10.1109/tmscs.2018.2829518

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

Author(s): Onur Tunali, Mustafa Altun
Published in: ACM Computing Surveys, Issue 50/6, 2018, Page(s) 1-35, ISSN 0360-0300
DOI: 10.1145/3125641

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Author(s): Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz
Published in: Microelectronics Journal, Issue 89, 2019, Page(s) 30-36, ISSN 0026-2692
DOI: 10.1016/j.mejo.2019.05.008

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Published in: 2017 Euromicro Conference on Digital System Design (DSD), 2017, Page(s) 137-144
DOI: 10.1109/DSD.2017.54

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
Published in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Page(s) 423-430
DOI: 10.1109/DSD.2016.75

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer

Author(s): Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
Published in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Page(s) 334-341
DOI: 10.1109/DSD.2016.45

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

Author(s): Muhammed Ceylan Morgul, Furkan Peker, Mustafa Altun
Published in: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, Page(s) 437-442
DOI: 10.1109/ISVLSI.2016.100

Synthesis on switching lattices of Dimension-reducible Boolean functions

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Published in: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Page(s) 1-6
DOI: 10.1109/VLSI-SoC.2016.7753577

Integrated Synthesis Methodology for Crossbar Arrays

Author(s): M. Ceylan Morgul, Dan Alexandrescu, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, E. Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan
Published in: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '18, 2018, Page(s) 91-97
DOI: 10.1145/3232195.3232211

Noise-induced Performance Enhancement of Variability-aware Memristor Networks

Author(s): Vasileios Ntinas, Iosif-Angelos Fyrigos, Georgios Ch. Sirakoulis, Antonio Rubio, Javier Martin-Martinez, Rosana Rodriguez, Montserrat Nafria
Published in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Page(s) 731-734
DOI: 10.1109/ICECS46596.2019.8965134

Analog Neural Network based on Memristor Crossbar Arrays

Author(s): Hacer A. Yildiz, Mustafa Altun, Ali Dogus Gungordu, Mircea R. Stan
Published in: 2019 11th International Conference on Electrical and Electronics Engineering (ELECO), 2019, Page(s) 358-361
DOI: 10.23919/eleco47770.2019.8990597

Testability of Switching Lattices in the Cellular Fault Model

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini
Published in: 2019 22nd Euromicro Conference on Digital System Design (DSD), 2019, Page(s) 320-327
DOI: 10.1109/dsd.2019.00054

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Author(s): Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Ioana Vatajelu
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704615

Testability of Switching Lattices in the Stuck at Fault Model

Author(s): Anna Bernasconi, Valentina Ciriani, Luca Frontini
Published in: 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, Page(s) 213-218
DOI: 10.1109/vlsi-soc.2018.8644806

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

Author(s): Onur Tunali, Mustafa Altun
Published in: 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017, Page(s) 534-537
DOI: 10.1109/icecs.2017.8292053

Spin-torque memristor based offset cancellation technique for sense amplifiers

Author(s): Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, Kaushik Roy
Published in: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, Page(s) 1-4
DOI: 10.1109/smacd.2017.7981595

Computing with Emerging Nanotechnologies

Author(s): M. Altun
Published in: Low-Dimensional and Nanostructured Materials and Devices, 2016, Page(s) 635-660
DOI: 10.1007/978-3-319-25340-4_26