Synthesis and Performance Optimization of a Switching Nano-crossbar Computer

Informazioni relative al progetto

NANOxCOMP

ID dell’accordo di sovvenzione: 691178

DOI

10.3030/691178

Progetto chiuso

Data della firma CE 5 Ottobre 2015

Data di avvio 1 Dicembre 2015

Data di completamento 30 Novembre 2019

Finanziato da

• EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions

Costo totale

€ 577 035,00

Contributo UE

€ 577 035,00

Coordinato da

ISTANBUL TEKNIK UNIVERSITESI
Türkiye

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Other (2)

Synthesis tool

Deliverable 1.1 - Software: A software tool synthesizing arrays with optimal sizes.

Performance optimization tool

Deliverable 2.1 - Software: A software tool having inputs of “defect rates”, “target Boolean functions”, and “required accuracy”, and an output of “crossbar size”.

Documents, reports (6)

Conference paper-2

Deliverable 4.1 - Publication: A paper submitted to a leading conference on computer-aided design (CAD) of digital circuits such as DAC, ASP-DAC, DATE, DDECS, NANOARCH, etc.

Patent and/or Journal paper-2

Deliverable 5.2 - Publication: A European patent filed and/or a paper submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Conference paper-1

Deliverable 1.2 - Publication: A paper submitted to a leading conference on computer-aided design (CAD) of digital circuits such as DAC, ASP-DAC, DATE, DDECS, NANOARCH, etc.

Journal papers

Deliverable 2.2 - Publication: At least two papers submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Report and/or Article

Deliverable 5.1 - Report/Article: A report/article on future directions of nano-crossbar based computing architectures is publicly released with lessons learned in this project.

Patent and/or Journal paper-1

Deliverable 4.2 - Publication: A European patent filed or a paper submitted to a leading journal on CAD of digital circuits such as relevant IEEE, ACM, Elsevier journals.

Pubblicazioni

Peer reviewed articles (10)

Logic synthesis and testing techniques for switching nano-crossbar arrays

Autori: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
Pubblicato in: Microprocessors and Microsystems, Numero 54, 2017, Pagina/e 14-25, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2017.08.004

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
Pubblicato in: Microprocessors and Microsystems, Numero 56, 2018, Pagina/e 193-203, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2017.12.003

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

Autori: Onur Tunali, Mustafa Altun
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numero 36-5, 2017, Pagina/e 1-1, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2016.2602804

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Autori: Levent Aksoy, Mustafa Altun
Pubblicato in: IEEE Transactions on Computers, Numero 69-3, 2019, Pagina/e 1-1, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2019.2950663

Composition of switching lattices for regular and for decomposed functions

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Pubblicato in: Microprocessors and Microsystems, Numero 60, 2018, Pagina/e 207-218, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2018.05.004

Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

Autori: M. Ceylan Morgül, Mustafa Altun
Pubblicato in: Integration, Numero 64, 2019, Pagina/e 60-70, ISSN 0167-9260
Editore: Elsevier BV
DOI: 10.1016/j.vlsi.2018.08.002

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Autori: Onur Tunali, M. Ceylan Morgul, Mustafa Altun
Pubblicato in: IEEE Micro, Numero 38/5, 2018, Pagina/e 22-31, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2018.053631138

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Autori: Furkan Peker, Mustafa Altun
Pubblicato in: IEEE Transactions on Multi-Scale Computing Systems, Numero 4/4, 2018, Pagina/e 522-532, ISSN 2332-7766
Editore: IEEE
DOI: 10.1109/tmscs.2018.2829518

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

Autori: Onur Tunali, Mustafa Altun
Pubblicato in: ACM Computing Surveys, Numero 50/6, 2018, Pagina/e 1-35, ISSN 0360-0300
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3125641

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Autori: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz
Pubblicato in: Microelectronics Journal, Numero 89, 2019, Pagina/e 30-36, ISSN 0026-2692
Editore: Mackintosh Publications
DOI: 10.1016/j.mejo.2019.05.008

Conference proceedings (17)

Computing with nano-crossbar arrays: Logic synthesis and fault tolerance

Autori: Mustafa Altun, Valentina Ciriani, Mehdi Tahoori
Pubblicato in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Pagina/e 278-281, ISBN 978-3-9815370-8-6
Editore: IEEE
DOI: 10.23919/DATE.2017.7926998

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Pubblicato in: 2017 Euromicro Conference on Digital System Design (DSD), 2017, Pagina/e 137-144, ISBN 978-1-5386-2146-2
Editore: IEEE
DOI: 10.1109/DSD.2017.54

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa
Pubblicato in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Pagina/e 423-430, ISBN 978-1-5090-2817-7
Editore: IEEE
DOI: 10.1109/DSD.2016.75

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer

Autori: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Tahoori
Pubblicato in: 2016 Euromicro Conference on Digital System Design (DSD), 2016, Pagina/e 334-341, ISBN 978-1-5090-2817-7
Editore: IEEE
DOI: 10.1109/DSD.2016.45

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

Autori: Muhammed Ceylan Morgul, Furkan Peker, Mustafa Altun
Pubblicato in: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, Pagina/e 437-442, ISBN 978-1-4673-9039-2
Editore: IEEE
DOI: 10.1109/ISVLSI.2016.100

Synthesis on switching lattices of Dimension-reducible Boolean functions

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco
Pubblicato in: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Pagina/e 1-6, ISBN 978-1-5090-3561-8
Editore: IEEE
DOI: 10.1109/VLSI-SoC.2016.7753577

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Autori: Serzat Safaltin, Oguz Gencer, M. Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, Mustafa Altun
Pubblicato in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Pagina/e 504-509, ISBN 978-3-9819263-2-3
Editore: IEEE
DOI: 10.23919/date.2019.8715123

Integrated Synthesis Methodology for Crossbar Arrays

Autori: M. Ceylan Morgul, Dan Alexandrescu, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, E. Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan
Pubblicato in: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '18, 2018, Pagina/e 91-97, ISBN 9781-450358156
Editore: ACM Press
DOI: 10.1145/3232195.3232211

Noise-induced Performance Enhancement of Variability-aware Memristor Networks

Autori: Vasileios Ntinas, Iosif-Angelos Fyrigos, Georgios Ch. Sirakoulis, Antonio Rubio, Javier Martin-Martinez, Rosana Rodriguez, Montserrat Nafria
Pubblicato in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Pagina/e 731-734, ISBN 978-1-7281-0996-1
Editore: IEEE
DOI: 10.1109/ICECS46596.2019.8965134

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Autori: Levent Aksoy, Mustafa Altun
Pubblicato in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Pagina/e 1637-1642, ISBN 978-3-9819263-2-3
Editore: IEEE
DOI: 10.23919/date.2019.8714809

Analog Neural Network based on Memristor Crossbar Arrays

Autori: Hacer A. Yildiz, Mustafa Altun, Ali Dogus Gungordu, Mircea R. Stan
Pubblicato in: 2019 11th International Conference on Electrical and Electronics Engineering (ELECO), 2019, Pagina/e 358-361, ISBN 978-605-01-1275-7
Editore: IEEE
DOI: 10.23919/eleco47770.2019.8990597

Testability of Switching Lattices in the Cellular Fault Model

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini
Pubblicato in: 2019 22nd Euromicro Conference on Digital System Design (DSD), 2019, Pagina/e 320-327, ISBN 978-1-7281-2862-7
Editore: IEEE
DOI: 10.1109/dsd.2019.00054

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Autori: Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Ioana Vatajelu
Pubblicato in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Pagina/e 1-6, ISBN 978-1-7281-1756-0
Editore: IEEE
DOI: 10.1109/latw.2019.8704615

Testability of Switching Lattices in the Stuck at Fault Model

Autori: Anna Bernasconi, Valentina Ciriani, Luca Frontini
Pubblicato in: 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, Pagina/e 213-218, ISBN 978-1-5386-4756-1
Editore: IEEE
DOI: 10.1109/vlsi-soc.2018.8644806

Logic synthesis and defect tolerance for memristive crossbar arrays

Autori: Onur Tunali, Mustafa Altun
Pubblicato in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Pagina/e 425-430, ISBN 978-3-9819263-0-9
Editore: IEEE
DOI: 10.23919/date.2018.8342047

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

Autori: Onur Tunali, Mustafa Altun
Pubblicato in: 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017, Pagina/e 534-537, ISBN 978-1-5386-1911-7
Editore: IEEE
DOI: 10.1109/icecs.2017.8292053

Spin-torque memristor based offset cancellation technique for sense amplifiers

Autori: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, Kaushik Roy
Pubblicato in: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, Pagina/e 1-4, ISBN 978-1-5090-5052-9
Editore: IEEE
DOI: 10.1109/smacd.2017.7981595

Book chapters (1)

Computing with Emerging Nanotechnologies

Autori: M. Altun
Pubblicato in: Low-Dimensional and Nanostructured Materials and Devices, 2016, Pagina/e 635-660, ISBN 978-3-319-25340-4
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-25340-4_26