In Lithography ASML and Zeiss addressed the challenges to meet the 5nm node requirements on image alignment and wafer throughput.
ASML developed a 5nm node lithographic scanner with a novel sensor that enables the system to measure wave-front aberrations. Other improvements that have been developed are its position measurement system, wafer stage and wafer handler as well as the optics. With the new 5nm node scanner first wafers exposures have been realized, demonstrating a 0.4nm full wafer Critical Dimension Uniformity, 1.1nm Matched Machine Overlay and a productivity of >145 wafers per hour.
Pre-development of the hyper NA EUV lithograph system has moved into the system design phase. One of the highlights is the demonstration of the working principle of local wafer cooling by ASML. This technology will be implemented to counteract the high heat load induced by the light eliminating the wafer.
Zeiss has developed a solid technological basis for manufacture of the new EUV illumination system. This comprises of many aspects ranging from the definition of the system specifications and the mechatronics for mirror control, all the way to the metrology and integration technology of the illumination system as a whole.
Metrology focused on patterning quality control equipment for the 5nm Node. In the project Applied Materials, FEI, KLA and Nova cooperated to improve measurement accuracy and through-put time by developing better sensors, light sources, scanning technology and enabling holistic solutions in which a multiple of metrology techniques are combined. Coventor and Fraunhofer have been involved in modeling and simulation of defect propagation in the optical path.
Over the course of the project productivity enhancement to the E-beam inspection/review PAD – Productivity Aware Design - tool of Applied Materials Israel, the PROVision ™ were realized. X-ray technologies from Bruker improved the overall characterization and productivity performance. New material characterization capability realized by Nova added relevant information to the traditional Optical Critical Dimension metrology. In Scanning Transmission Electron Microscope FEI realized faster throughput. KLA Israel made progress in exploring overlay accuracy enhancements with a new target design for 5nm. All the companies qualified successfully their tools with imec’s 5nm node representative wafer samples.
In Process Technology 5nm node patterning was explored and demonstrated. Subjects, addressed by imec, ASM-Belgium and Coventor, covered are design rules, patterning, creation of new self-aligned schemes including area selective deposition approaches, Direct Self Assembly, Middle of Line and Back end of Line technology solutions.
A final set of design rules for the 5nm technology node was created with a most aggressive pitch for metal interconnect of 21nm which still allows for Deep UV multi-patterning lithography. For other critical layers such as Cut, Via and Block patterning, migrating to EUV multi-patterning is required.
To further reduce area, new fully Self-Aligned Contact (fSAC), Self-Aligned Gate Contact (SAGC) and Fully Self-Aligned Via (FSAV) have been realized.
On Area Selective Deposition (ASD) Selective growth of dielectric on SAM passivated wafers at the most aggressive 5nm node pitch of 21nm was demonstrated.
In Direct Self Assembly the defectivity levels were reduced to less 100/cm2 and Via pairs at 28nm pitch were realized.
In the middle- and back-end of line a new 3 metal-level integration mask was designed with dual damascene patterning co-integrated with low k spacers, Local interconnect, self-aligned contact to active metal-plug and self-aligned contact to replacement metal gate.
