Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design

Risultati finali

ESR4.1 IRP EDA tools and methodologies for reliable nanoelectronic systems

"D4.1 reports on progress of WP4 IRP ""EDA tools and methodologies for reliable nanoelectronic systems"" corresponding to task T4.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR4.3 IRP Open-source EDA tools for design quality and reliability using zamiaCAD

"D4.3 reports on progress of WP4 IRP ""Open-source EDA tools for design quality and reliability using zamiaCAD"" corresponding to task T4.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.2 IRP Design approaches for tamper resistant crypto implementations

"D3.2 reports on progress of WP3 IRP ""Design approaches for tamper resistant crypto implementations"" corresponding to task T3.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.3 IRP HW/SW fault tolerance methods driven by reliability and timing constraints

"D1.3 reports on progress of WP1 IRP ""HW/SW fault tolerance methods driven by reliability and timing constraints"" corresponding to task T1.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.3 IRP Side-channel and Fault Attack resistant security primitives design

"D3.3 reports on progress of WP3 IRP ""Side-channel and Fault Attack resistant security primitives design"" corresponding to task T3.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Comprehensive Communication Plan

Comprehensive Communication Plan to map main target groups and dissemination plan.

ESR2.2 IRP Innovative real-time operating system for error management for single- and multi-core units

"D2.2 reports on progress of WP2 IRP ""Innovative real-time operating system for error management for single- and multi-core units"" corresponding to task T2.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR4.2 IRP EDA tools and methodologies for high quality nanoelectronic systems

"D4.2 reports on progress of WP4 IRP ""EDA tools and methodologies for high quality nanoelectronic systems"" corresponding to task T4.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.5 IRP Reliable operation infrastructure for dynamic, high-dependability applications

"D1.1 reports on progress of WP1 IRP ""Reliable operation infrastructure for dynamic, high-dependability applications"" corresponding to task T1.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.4 IRP Techniques for detecting permanent faults during the operational phase

"D1.4 reports on progress of WP1 IRP ""Techniques for detecting permanent faults during the operational phase"" corresponding to task T1.4. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Report on Dissemination and Communication activities

Report on dissemination and Communication activities throughout the whole project.

ESR3.1 IRP A novel Physical Unclonable Functions technology

"D3.1 reports on progress of WP3 IRP ""A novel Physical Unclonable Functions technology"" corresponding to task T3.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.2 IRP Adaptive methods for fault tolerant embedded systems

"D1.2 reports on progress of WP1 IRP ""Adaptive methods for fault tolerant embedded systems"" corresponding to task T1.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Reports on training events

Brief reports presenting the main training outcomes. Intermediate versions of the deliverable are due by M18 and M30.

ESR2.1 IRP Effective techniques for secure and reliable systems validation

"D2.1 reports on progress of WP2 IRP ""Effective techniques for secure and reliable systems validation"" corresponding to task T2.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Report on recruitment process

Report on recruitment process and the recruited fellows enrolment in PhD programme

ESR1.1 IRP Reliability analysis methods and models of memory devices

"D1.1 reports on progress of WP1 IRP ""Reliability analysis and modelling of memory devices"" corresponding to task T1.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Supervisory board of the network

Establish the Supervisory board of the network.

ESR2.3 IRP A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability

"D2.3 reports on progress of WP2 IRP ""A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability"" corresponding to task T2.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR2.4 IRP Design errors verification and debug methods for complex nanoelectronic systems

"D2.4 reports on progress of WP2 IRP ""Design errors verification and debug methods for complex nanoelectronic systems"" corresponding to task T2.4. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Website, project logo and wiki-type online collaboration tool

Website, project logo and wiki-type online collaboration tool as for main dissemination.

Articles published

40 scientific articles, 10 technical reports and 4 popular science articles will be published.

Pubblicazioni

New categories of Safe Faults in a processor-based Embedded System

Autori: C. Gursoy, M. Jenihhin, A. S. Oyeniran, D. Piumatti, J. Raik, M. Sonza Reorda, R. Ubar
Pubblicato in: 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, Pagina/e 1-4, ISBN 978-1-7281-0073-9
Editore: IEEE
DOI: 10.1109/ddecs.2019.8724642

Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

Autori: Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Sandro Sartoni, Riccardo Cantoro, Matteo Sonza Reorda, Said Hamdioui, Christian Sauer
Pubblicato in: 2020 IEEE European Test Symposium (ETS), 2020, Pagina/e 1-6, ISBN 978-1-7281-4312-5
Editore: IEEE
DOI: 10.1109/ets48528.2020.9131568

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Autori: Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Pubblicato in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Pagina/e 1-7, ISBN 978-1-7281-8187-5
Editore: IEEE
DOI: 10.1109/iolts50870.2020.9159751

Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness

Autori: R. Segabinazzi Ferreira, N. George, J. Chen, M. Hübner, M. Krstic, J. Nolte, and H. T. Vierhaus
Pubblicato in: 2019
Editore: DSD
DOI: 10.26127/btuopen-5050

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Autori: Guilherme Cardoso Medeiros, Cemil Cem Gursoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui
Pubblicato in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Pagina/e 792-797, ISBN 978-3-9819263-4-7
Editore: IEEE
DOI: 10.23919/date48585.2020.9116278

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Autori: Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Pubblicato in: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2019, Pagina/e 1-6, ISBN 978-1-7281-3424-6
Editore: IEEE
DOI: 10.1109/dtis.2019.8735052

Untestable faults identification in GPGPUs for safety-critical applications

Autori: Josie E. Rodriguez Condia, Felipe A. Da Silva, S. Hamdioui, C. Sauer, M. Sonza Reorda
Pubblicato in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Pagina/e 570-573, ISBN 978-1-7281-0996-1
Editore: IEEE
DOI: 10.1109/icecs46596.2019.8964677

On the in-field test of the GPGPU scheduler memory

Autori: Stefano di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda
Pubblicato in: 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, Pagina/e 1-6, ISBN 978-1-7281-0073-9
Editore: IEEE
DOI: 10.1109/ddecs.2019.8724672

Real-Time Dynamic Hardware Reconfiguration for Processors with Redundant Functional Units

Autori: Randolf Rotta, Raphael Segabinazzi Ferreira, Jorg Nolte
Pubblicato in: 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC), 2020, Pagina/e 154-155, ISBN 978-1-7281-6958-3
Editore: IEEE
DOI: 10.1109/isorc49007.2020.00035

"""Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits"""

Autori: T. Lange, A. Balakrishnan, M. Glorieux, D. Alexandrescu, L. Sterpone
Pubblicato in: 2019
Editore: SEÖSE

On the functional test of the GPGPU scheduler

Autori: J. E. Rodriguez Condia, B. Du, M. Sonza Reorda, L. Sterpone
Pubblicato in: 2018
Editore: Harwell Campus
DOI: 10.5281/zenodo.4662619

Metal Fillers as Potential Low Cost Countermeasure against Optical Fault Injection Attacks

Autori: Dmytro Petryk, Zoya Dyka, Jens Katzer, Peter Langendorfer
Pubblicato in: 2020 IEEE East-West Design & Test Symposium (EWDTS), 2020, Pagina/e 1-6, ISBN 978-1-7281-9899-6
Editore: IEEE
DOI: 10.1109/ewdts50664.2020.9225092

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

Autori: Xinhui Lai, Maksim Jenihhin, Georgios Selimis, Sven Goossens, Roel Maes, Kolin Paul
Pubblicato in: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, Pagina/e 16-21, ISBN 978-1-7281-5409-1
Editore: IEEE
DOI: 10.1109/vlsi-soc46417.2020.9344071

Laser Fault Injection Attacks against IHP Chips

Autori: D. Petryk, Z. Dyka, P. Langendörfer
Pubblicato in: 2021
Editore: in32. Krypto-Tag 1st Digital Summit
DOI: 10.18420/cdm-2021-32-22

Detecting Random Read Faults to Reduce Test Escapes in FinFETSRAMs

Autori: G. C. Medeiros, M. Fieback, M. Taouil, L. B. Poehls, and S. Hamdioui
Pubblicato in: 2021
Editore: IEEE

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

Autori: M. Jenihhin, S. Hamdioui, M. Sonza Reorda, M. Krstic, P. Langendorfer, C. Sauer, A. Klotz, M. Huebner, J. Nolte, H. T. Vierhaus, G. Selimis, D. Alexandrescu, M. Taouil, G. J. Schrijen, J. Raik, L. Sterpone, G. Squillero, Z. Dyka
Pubblicato in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Pagina/e 388-393, ISBN 978-3-9819263-4-7
Editore: IEEE
DOI: 10.23919/date48585.2020.9116558

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Autori: T. Copetti, G. C. Medeiros, M. Taouil, S. Hamdioui, L. B. Poehls and T. Balen
Pubblicato in: 2020
Editore: 2020 IEEE Latin-American Test Symposium (LATS)
DOI: 10.1109/lats49555.2020.9093667

Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction

Autori: J. Chen, T. Lange, M. Andjelkovic, A. Simevski, M. Krstic
Pubblicato in: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020, Pagina/e 1-6, ISBN 978-1-7281-9457-8
Editore: IEEE
DOI: 10.1109/dft50435.2020.9250856

Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy

Autori: Josie E Rodriguez Condia, M. Sonza Reorda
Pubblicato in: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, Pagina/e 153-158, ISBN 978-1-7281-5409-1
Editore: IEEE
DOI: 10.1109/vlsi-soc46417.2020.9344088

Design and Verification of an open-source SFU model for GPGPUs

Autori: Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Cristhian-Fernando Moreno-Manrique, Matteo Sonza Reorda
Pubblicato in: 2020 17th Biennial Baltic Electronics Conference (BEC), 2020, Pagina/e 1-6, ISBN 978-1-7281-9444-8
Editore: IEEE
DOI: 10.1109/bec49624.2020.9276748

On the testing of special memories in GPGPUs

Autori: Josie E. Rodriguez Condia, Matteo Sonza Reorda
Pubblicato in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Pagina/e 1-6, ISBN 978-1-7281-8187-5
Editore: IEEE
DOI: 10.1109/iolts50870.2020.9159711

Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems

Autori: J. Chen, M. Andjelkovic, A. Simevski, Y. Li, P. Skoncej and M. Krstic
Pubblicato in: 2019
Editore: DSD
DOI: 10.1109/dsd.2019.00080

Efficient Fault Injection based on Dynamic HDL Slicing Technique

Autori: Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
Pubblicato in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Pagina/e 52-53, ISBN 978-1-7281-2490-2
Editore: IEEE
DOI: 10.1109/iolts.2019.8854419

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

Autori: Marcio M. Goncalves, Jose Rodrigo Azambuja, Josie E. R. Condia, Matteo Sonza Reorda, Luca Sterpone
Pubblicato in: 2020 IEEE Latin-American Test Symposium (LATS), 2020, Pagina/e 1-6, ISBN 978-1-7281-8731-0
Editore: IEEE
DOI: 10.1109/lats49555.2020.9093682

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs

Autori: Josie E. Rodriguez Condia, Pierpaolo Narducci, M. Sonza Reorda, L. Sterpone
Pubblicato in: 2020 IEEE 38th VLSI Test Symposium (VTS), 2020, Pagina/e 1-6, ISBN 978-1-7281-5359-9
Editore: IEEE
DOI: 10.1109/vts48691.2020.9107572

On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks

Autori: Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Guursoy, Maksim Jenihhin
Pubblicato in: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, Pagina/e 335-340, ISBN 978-1-7281-3915-9
Editore: IEEE
DOI: 10.1109/vlsi-soc.2019.8920313

Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications

Autori: Raphael Segabinazzi Ferreira, Jorg Nolte, Fabian Vargas, Nevin George, Michael Hubner
Pubblicato in: 2020 IEEE Latin-American Test Symposium (LATS), 2020, Pagina/e 1-6, ISBN 978-1-7281-8731-0
Editore: IEEE
DOI: 10.1109/lats49555.2020.9093692

Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models

Autori: Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux
Pubblicato in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Pagina/e 1-6, ISBN 978-1-7281-8187-5
Editore: IEEE
DOI: 10.1109/iolts50870.2020.9159750

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

Autori: Josie E. Rodriguez Condia, Pierpaolo Narducci, M. Sonza Reorda, L. Sterpone
Pubblicato in: 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020, Pagina/e 1-6, ISBN 978-1-7281-9938-2
Editore: IEEE
DOI: 10.1109/ddecs50862.2020.9095665

Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification

Autori: Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer
Pubblicato in: 2019 IEEE 28th Asian Test Symposium (ATS), 2019, Pagina/e 129-1295, ISBN 978-1-7281-2695-1
Editore: IEEE
DOI: 10.1109/ats47505.2019.00024

Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

Autori: Josie E. Rodriguez Condia, Marcio M. Goncalves, Jose Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone
Pubblicato in: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Pagina/e 380-385, ISBN 978-1-7281-5775-7
Editore: IEEE
DOI: 10.1109/isvlsi49217.2020.00076

Improving GPU Register File Reliability with a comprehensive ISA extension

Autori: M. M. Goncalves; Josie E. Rodriguez Condia; M. Sonza Reorda, L. Sterpone and J. R. Azambuja
Pubblicato in: 2020
Editore: ESREF
DOI: 10.5281/zenodo.4662676

Modeling Static Noise Margin for FinFET based SRAM PUFs

Autori: S. Masoumian, G. Selimis, R. Maes, G. Schrijen, S. Hamdioui and M. Taouil
Pubblicato in: 2020 IEEE European Test Symposium (ETS), 2020, Pagina/e pp. 1-6.
Editore: IEEE
DOI: 10.1109/ets48528.2020.9131583

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

Autori: T. Lange, A. Balakrishnan, M. Glorieux, D. Alexandrescu and L. Sterpone,
Pubblicato in: 2019
Editore: IEEE
DOI: 10.1109/dsn-s.2019.00021

Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach

Autori: Josie E. Rodriguez Condia, Matteo Sonza Reorda
Pubblicato in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Pagina/e 97-102, ISBN 978-1-7281-2490-2
Editore: IEEE
DOI: 10.1109/iolts.2019.8854463

Design of Radiation Hardened RADFET Readout System for Space Applications

Autori: M. Andjelkovic, A. Simevski, J. Chen, M. Krstic, et al.
Pubblicato in: 23rd Euromicro Conference on Digital System Design (DSD), 2020
Editore: IEEE
DOI: 10.1109/dsd51259.2020.00082

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Autori: Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
Pubblicato in: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019, Pagina/e 1-7, ISBN 978-1-7281-2769-9
Editore: IEEE
DOI: 10.1109/norchip.2019.8906932

An open source embedded-GPGPU model for the accurate analysis and mitigation of SEU effects

Autori: B. Du; J. E. Rodriguez Condia; M. Sonza Reorda; L. Sterpone
Pubblicato in: 2019
Editore: RADECS
DOI: 10.5281/zenodo.4662662

A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores

Autori: Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sanchez, Giovanni Squillero
Pubblicato in: 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2021, Pagina/e 51-56, ISBN 978-1-6654-3595-6
Editore: IEEE
DOI: 10.1109/ddecs52668.2021.9417061

About the functional test of the GPGPU scheduler

Autori: B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Pubblicato in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Numero Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain, July 2-4, 2018, 2018, Pagina/e 85-90, ISBN 978-1-5386-5992-2
Editore: IEEE
DOI: 10.1109/IOLTS.2018.8474174

On the functional test of the GPGPU scheduler

Autori: Josie E. Rodriguez Condia, B. Du, M. Sonza Reorda, L. Sterpone
Pubblicato in: A workshop on Self-driving Cars and Reliability, Rutherford Appleton Laboratory, Harwell Campus, 2018
Editore: A workshop on Self-driving Cars and Reliability, Rutherford Appleton Laboratory, Harwell Campus

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

Autori: Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Pubblicato in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Pagina/e 55-60, ISBN 978-1-5386-5180-3
Editore: IEEE
DOI: 10.1109/ITC-Asia.2018.00020

Optical Fault Injections: Most Often Used Setups

Autori: D. Petryk, Z. Dyka, P. Langendörfer
Pubblicato in: Proc. 29th Crypto-Day 2018, 2018
Editore: 29. Krypto-Tag / Proc. 29th Crypto-Day 2018
DOI: 10.18420/cdm-2018-29-11

Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

Autori: F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer
Pubblicato in: 2018 Design and Verification conference Europe (DVCON-Europe), 2018
Editore: 2018 Design and Verification Conference and Exhibition (DVCon) Europe
DOI: 10.5281/zenodo.3361533

Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

Autori: A. C. Bagbaba, F. Augusto da Silva, C. Sauer
Pubblicato in: 2018 Design and Verification conference Europe (DVCON-Europe), 2018
Editore: 2018 Design and Verification Conference and Exhibition (DVCon) Europe
DOI: 10.5281/zenodo.3361607

Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA

Autori: Thomas Lange, Maximilien Glorieux, Adrian Evans, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Carlos Urbina Ortega, Véronique Ferlet-Cavrois, Maris Tali, Rubén Garcı́a Alı́a
Pubblicato in: 2018 ESA/ESTEC Space FPGA Users Workshop (SEFUW), 2018
Editore: 2018 ESA/ESTEC Space FPGA Users Workshop (SEFUW)

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Autori: Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs
Pubblicato in: 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2018, Pagina/e 120-126, ISBN 978-1-5386-7753-7
Editore: IEEE
DOI: 10.1109/AHS.2018.8541474

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Autori: Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, Leticia Bolzani Poehls, Said Hamdioui
Pubblicato in: 2019 IEEE European Test Symposium (ETS), 2019, Pagina/e 1-2, ISBN 978-1-7281-1173-5
Editore: IEEE
DOI: 10.1109/ets.2019.8791517

On the evaluation of SEU effects in GPGPUs

Autori: B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Pubblicato in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Pagina/e 1-6, ISBN 978-1-7281-1756-0
Editore: IEEE
DOI: 10.1109/latw.2019.8704643

An extended GPGPU model to support detailed reliability analysis

Autori: Josie E. Rodriguez Condia, Matteo Sonza Reorda
Pubblicato in: SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects, Numero 27-28 March 2019, Stanford, California, USA, 2019
Editore: SELSE-15

IN-FIELD GPGPU TEST WITH SBST TECHNIQUES

Autori: B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Pubblicato in: NVIDIA GPU Tecnology Conference (GTC Europe 2018), Numero 23-25 October, 2018, Munich, Germany, 2018
Editore: GTC Europe 2018

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Autori: Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Pubblicato in: 2018 IEEE International Test Conference (ITC), 2018, Pagina/e 1-9, ISBN 978-1-5386-8382-8
Editore: IEEE
DOI: 10.1109/test.2018.8624742

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Autori: A. Damljanovic, A. Jutman, G. Squillero and A. Tsertov
Pubblicato in: Proc. IEEE European Test Symposium 2019 (in press), 2019
Editore: IEEE
DOI: 10.5281/zenodo.3362602

Comparing different approaches to the test of Reconfigurable Scan Networks

Autori: R. Cantoro, A.Damljanovic. M. Sonza Reorda and G. Squillero
Pubblicato in: 2018 3rd International Test Standards Application Workshop (TESTA), 2018
Editore: 2018 3rd International Test Standards Application Workshop (TESTA)

Single-Event Characterization of Xilinx UltraScale+ ® MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation

Autori: Maximilien Glorieux, Adrian Evans, Thomas Lange, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Ruben Garcia Alia, Maris Tali, Carlos Urbina Ortega, Maria Kastriotou, Pablo Fernandez-Martinez, Veronique Ferlet-Cavrois
Pubblicato in: 2018 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2018), 2018, Pagina/e 1-5, ISBN 978-1-5386-8263-0
Editore: IEEE
DOI: 10.1109/nsrec.2018.8584296

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Autori: Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
Pubblicato in: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, Pagina/e 1-7, ISBN 978-1-5386-7656-1
Editore: IEEE
DOI: 10.1109/norchip.2018.8573495

Mixed-level identification of fault redundancy in microprocessors

Autori: Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
Pubblicato in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Pagina/e 1-6, ISBN 978-1-7281-1756-0
Editore: IEEE
DOI: 10.1109/latw.2019.8704591

Software-Based Mitigation for Memory Address Decoder Aging

Autori: D.H.P. Kraak, C.C. Gursoy, I.O. Agbo, M. Taouil, M. Jenihhin, J. Raik, S. Hamdioui
Pubblicato in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Pagina/e 1-6, ISBN 978-1-7281-1756-0
Editore: IEEE
DOI: 10.1109/latw.2019.8704595

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Autori: Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Pubblicato in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Pagina/e 7-14, ISBN 978-1-7281-2490-2
Editore: IEEE
DOI: 10.1109/iolts.2019.8854423

RESCUE EDA Toolset for Interdependent Aspects of Reliability, Security and Quality in Nanoelectronic Systems Design

Autori: C. C. Gürsoy, G. Medeiros, J. Chen, N. George, J. E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. da Silva, A. Bagbaba, S. Hamdioui, M. Taouil, M. Krstic, P. Langendörfer, Z. Dyka, M. Huebner, J. Nolte, H. T. Vierhaus,M. Sonza Reorda, G. Squillero, L. Sterpone, J. Raik, D. Alexandrescu, M. Glorieux, G. Selimis
Pubblicato in: University Booth - Design, Automation & Test in Europe Conference & Exhibition (Univerity Booth DATE 2019), Numero 25-29 March 2019, 2019
Editore: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
DOI: 10.5281/zenodo.3362529

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Autori: Adeboye Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
Pubblicato in: Proc. IEEE European Test Symposium 2019 (in press), 2019
Editore: IEEE

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality

Autori: Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
Pubblicato in: 2018 12th European Workshop on Microelectronics Education (EWME), 2018, Pagina/e 45-50, ISBN 978-1-5386-9114-4
Editore: IEEE
DOI: 10.1109/ewme.2018.8629465

A Particle Detector Based on Pulse Stretching Inverter Chain

Autori: Marko Andjelkovic, Mitko Veleski, Junchao Chen, Aleksandar Simevski, Milos Krstic, Rolf Kraemer
Pubblicato in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Pagina/e 594-597, ISBN 978-1-7281-0996-1
Editore: IEEE
DOI: 10.1109/icecs46596.2019.8964644

Error Rate Calculation of Functional Failures Induced by Single-Event Transients in Clock Distribution Networks

Autori: T. Lange; M. Glorieux; D. Alexandrescu; L. Sterpone
Pubblicato in: 2020
Editore: SEE/MAPLD

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL

Autori: Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sanchez, Giovanni Squillero, Anton Tsertov
Pubblicato in: 2019 IEEE International Test Conference (ITC), 2019, Pagina/e 1-8, ISBN 978-1-7281-4823-6
Editore: IEEE
DOI: 10.1109/itc44170.2019.9000181

RNN-Based Detection of Fault Attacks on RSA

Autori: Troya Cagail Koylu, Cezar Rodolfo Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil
Pubblicato in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, Pagina/e 1-5, ISBN 978-1-7281-3320-1
Editore: IEEE
DOI: 10.1109/iscas45731.2020.9180708

Efficient Methodology for ISO26262 Functional Safety Verification

Autori: Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer
Pubblicato in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Pagina/e 255-256, ISBN 978-1-7281-2490-2
Editore: IEEE
DOI: 10.1109/iolts.2019.8854449

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL

Autori: Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
Pubblicato in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Pagina/e 1-6, ISBN 978-1-7281-8187-5
Editore: IEEE
DOI: 10.1109/iolts50870.2020.9159715

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Autori: Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sanchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer
Pubblicato in: 2020 IEEE 38th VLSI Test Symposium (VTS), 2020, Pagina/e 1-9, ISBN 978-1-7281-5359-9
Editore: IEEE
DOI: 10.1109/vts48691.2020.9107599

Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks

Autori: Dmytro Petryk, Zoya Dyka, Eduardo Perez, Mamathamba Kalishettyhalli Mahadevaiaha, Ievgen Kabin, Christian Wenger, Peter Langendorfer
Pubblicato in: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Pagina/e 238-245, ISBN 978-1-7281-9535-3
Editore: IEEE
DOI: 10.1109/dsd51259.2020.00047

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

Autori: Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
Pubblicato in: 2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2019, Pagina/e 72-78, ISBN 978-1-7281-4650-8
Editore: IEEE
DOI: 10.1109/ahs.2019.00007

PASCAL: Timing SCA Resistant Design and Verification Flow

Autori: Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
Pubblicato in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Pagina/e 239-242, ISBN 978-1-7281-2490-2
Editore: IEEE
DOI: 10.1109/iolts.2019.8854458

Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters

Autori: M. Andjelkovic, J. Chen, A. Simevski, Z. Stamenkovic, M. Krstic, R. Kraemer
Pubblicato in: Proc. 31st European Conference on Radiation and its Effects on Components and Systems, 2020
Editore: IEEE

Low latency reconfiguration mechanism for fine-grained processor internal functional units

Autori: Raphael Segabinazzi Ferreira, Jorg Nolte
Pubblicato in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Pagina/e 1-6, ISBN 978-1-7281-1756-0
Editore: IEEE
DOI: 10.1109/latw.2019.8704560

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Autori: Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
Pubblicato in: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019, Pagina/e 1-6, ISBN 978-1-7281-2260-1
Editore: IEEE
DOI: 10.1109/dft.2019.8875379

Sensitivity of Standard Library Cells to Optical Fault Injection Attacks in IHP 250 nm Technology

Autori: Dmytro Petryk, Zoya Dyka, Peter Langendorfer
Pubblicato in: 2020 9th Mediterranean Conference on Embedded Computing (MECO), 2020, Pagina/e 1-4, ISBN 978-1-7281-6949-1
Editore: IEEE
DOI: 10.1109/meco49872.2020.9134146

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

Autori: Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
Pubblicato in: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019, Pagina/e 1-7, ISBN 978-1-7281-2769-9
Editore: IEEE
DOI: 10.1109/norchip.2019.8906974

An extended model to support detailed GPGPU reliability analysis

Autori: B. Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda
Pubblicato in: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2019, Pagina/e 1-6, ISBN 978-1-7281-3424-6
Editore: IEEE
DOI: 10.1109/dtis.2019.8735047

Towards the Use of Machine Learning to Estimate the Functional Failure Rate of Complex Circuits

Autori: T. Lange; A. Balakrishnan; M. Glorieux; D. Alexandrescu; L. Sterpone
Pubblicato in: 2020
Editore: No

RESCUED: A Rescue Demonstrator for Interdependent Aspects of Reliability, Security and Quality Towards a Complete EDA Flow

Autori: C.C. Gursoy, G. Medeiros, J. Chen, N. George, J.E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. da Silva, A. Bagbaba, S.Hamdioui, M.Taouil, M.Krstic, P.Langend ̈orfer, Z.Dyka, M.Brandalero, M.H ̈ubner, J.N ̈olte, H.T.Vierhaus, M.Sonza Reorda, G.Squillero, L.Sterpone, J.Raik, D.Alexandrescu, M.Glorieux, G.Seli
Pubblicato in: 2020
Editore: DATE

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

Autori: Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Pubblicato in: Journal of Circuits, Systems and Computers, Numero 28/supp01, 2019, Pagina/e 1940007, ISSN 0218-1266
Editore: World Scientific Publishing Co
DOI: 10.1142/s0218126619400073

Understanding multidimensional verification: Where functional meets non-functional

Autori: Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu
Pubblicato in: Microprocessors and Microsystems, Numero 71, 2019, Pagina/e 102867, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2019.102867

FlexGripPlus: An improved GPGPU model to support reliability analysis

Autori: Josie E. RodriguezCondia, Boyang Du, Matteo Sonza Reorda, Luca Sterpone
Pubblicato in: Microelectronics Reliability, 2020, ISSN 0026-2714
Editore: Elsevier BV
DOI: 10.1016/j.microrel.2020.113660

"""Improving GPU Register File Reliability with a comprehensive ISA extension"""

Autori: M. M. Goncalves; Josie E. Rodriguez Condia; M. Sonza Reorda, L. Sterpone and J. R. Azambuja
Pubblicato in: Microelectronics Reliability, Numero Volume 114, November 2020 113768, 2020, ISSN 0026-2714
Editore: Elsevier BV
DOI: 10.1016/j.microrel.2020.113768

Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning

Autori: J. Chen, T. Lange, M. Andjelkovic, A. Simevski, M. Krstic
Pubblicato in: Microelectronics Reliability, Numero 114, 2020, Pagina/e 113799, ISSN 0026-2714
Editore: Elsevier BV
DOI: 10.1016/j.microrel.2020.113799

DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability

Autori: Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
Pubblicato in: The Journal of Supercomputing, 2021, ISSN 0920-8542
Editore: Kluwer Academic Publishers
DOI: 10.1007/s11227-021-03751-2

An on-line testing technique for the scheduler memory of a GPGPU

Autori: S. Di Carlo, J. E. Rodriguez Condia and M. Sonza Reorda
Pubblicato in: IEEE Access, 2020, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.2968139

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Autori: G.C. Medeiros, L.M. Bolzani Poehls, M. Taouil, F. Luis Vargas, S. Hamdioui
Pubblicato in: Microelectronics Reliability, Numero 88-90, 2018, Pagina/e 355-359, ISSN 0026-2714
Editore: Elsevier BV
DOI: 10.1016/j.microrel.2018.07.092

Double cell upsets mitigation through triple modular redundancy

Autori: Yuanqing Li, Anselm Breitenreiter, Marko Andjelkovic, Junchao Chen, Milan Babic, Milos Krstic
Pubblicato in: Microelectronics Journal, Numero 96, 2020, Pagina/e 104683, ISSN 0026-2692
Editore: Mackintosh Publications
DOI: 10.1016/j.mejo.2019.104683

Design techniques to improve the resilience of computing systems: software layer

Autori: A. Bosio; S. Di Carlo; G. Di Natale; M. Sonza Reorda and Josie E. Rodriguez Condia
Pubblicato in: Cross-Layer Reliability of Computing Systems, 2020
Editore: Cross-Layer Reliability of Computing Systems
DOI: 10.5281/zenodo.4664277

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