Memristive In-Memory Processing System

Informazioni relative al progetto

Real-PIM-System

ID dell’accordo di sovvenzione: 757259

DOI

10.3030/757259

Progetto chiuso

Data della firma CE 6 Dicembre 2017

Data di avvio 1 Gennaio 2018

Data di completamento 31 Dicembre 2023

Finanziato da

• EXCELLENT SCIENCE - European Research Council (ERC)

Costo totale

€ 1 500 000,00

Contributo UE

€ 1 500 000,00

Coordinato da

TECHNION - ISRAEL INSTITUTE OF TECHNOLOGY
Israel

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Pubblicazioni

Conference proceedings (20)

Making Memristive Processing-in-Memory Reliable

Autori: Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky
Pubblicato in: 28th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2021, ISBN 978-1-7281-8281-0
Editore: IEEE
DOI: 10.1109/icecs53924.2021.9665596

Making Real Memristive Processing-in-Memory Faster and Reliable

Autori: Shahar Kvatinsky
Pubblicato in: International Cellular Nanoscale Networks and their Applications, 2021, Pagina/e pp. 1-3, ISBN 978-1-6654-3948-0
Editore: IEEE
DOI: 10.1109/cnna49188.2021.9610786

Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory

Autori: Ben Perach, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IEEE interregional NEWCAS Conference, 2023
Editore: IEEE

A Pipelined Memristive Neural Network Analog-to-Digital Converter

Autori: Loai Danial, Kanishka Sharma, Shahar Kvatinsky
Pubblicato in: IEEE International Symposium on Circuits and Systems (ISCAS), 2020
Editore: IEEE
DOI: 10.1109/iscas45731.2020.9181108

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory

Autori: Orian Leitersdorf; Ben Perach; Ronny Ronen; Shahar Kvatinsky
Pubblicato in: 58th ACM/IEEE Design Automation Conference (DAC), 2021, ISBN 978-1-6654-3274-0
Editore: IEEE
DOI: 10.1109/dac18074.2021.9586324

On Consistency for Bulk-Bitwise Processing-in-Memory

Autori: B. Perach, R. Ronen, and S. Kvatinsky
Pubblicato in: IEEE/ACM International Symposium on High-Performance Computer Architecture, 2023
Editore: IEEE

Enhancing Security of Memristor Computing System Through Secure Weight Mapping

Autori: Minhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang, Shahar Kvatinsky
Pubblicato in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022
Editore: IEEE

Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM

Autori: Barak Hoffer, Shahar Kvatinsky
Pubblicato in: IEEE International Conference on Nanotechnology (NANO), 2022
Editore: IEEE

FiltPIM: In-Memory Filter for DNA Sequencing

Autori: Marcel Khalifa, Rotem Ben-Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits and Shahar Kvatinsky
Pubblicato in: IEEE International Conference on Electronics Circuits and Systems (ICECS), 2021, Pagina/e pp. 1-6, ISBN 978-1-7281-8281-0
Editore: IEEE
DOI: 10.1109/icecs53924.2021.9665570

abstractPIM: Bridging the Gap Between PIM Technology and ISA

Autori: Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatnsky
Pubblicato in: IFIP/IEEE VLSI-SoC, 2020, Pagina/e pp. 28-33, ISBN 978-1-7281-5409-1
Editore: IEEE
DOI: 10.1109/vlsi-soc46417.2020.9344103

MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic

Autori: Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: International Symposium on Circuits and Systems, 2022
Editore: IEEE

X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities

Autori: Natan Peled; Rotem Ben-Hur; Ronny Ronen; Shahar Kvatinsky
Pubblicato in: IFIP/IEEE VLSI-SoC, Numero 1, 2020
Editore: IEEE
DOI: 10.5281/zenodo.4023241

Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC

Autori: Ameer Haj-Ali, Rotem Ben-Hur, Nimrod Wald, Shahar Kvatinsky
Pubblicato in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Pagina/e 1-5, ISBN 978-1-5386-4881-0
Editore: IEEE
DOI: 10.1109/iscas.2018.8351561

Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)

Autori: Shahar Kvatinsky
Pubblicato in: 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, Pagina/e 142-148, ISBN 978-1-7281-1601-3
Editore: IEEE
DOI: 10.1109/asap.2019.00-10

A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors

Autori: Nicolas Wainstein, Tamir Tsabari, Yarden Goldin, Eilam Yalon, Shahar Kvatinsky
Pubblicato in: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, Pagina/e 290-295, ISBN 978-1-7281-3391-1
Editore: IEEE
DOI: 10.1109/isvlsi.2019.00060

Performing Memristor-Aided Logic (MAGIC) using STT-MRAM

Autori: Jeffry Louis, Barak Hoffer, Shahar Kvatinsky
Pubblicato in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Pagina/e 787-790, ISBN 978-1-7281-0996-1
Editore: IEEE
DOI: 10.1109/icecs46596.2019.8965179

X-MAGIC: Enhancing PIM using Input-Overwriting Capabilities

Autori: Natan Peled, Rotem Ben-Hur, Ronny Ronen, Shahar vatinsky
Pubblicato in: 2020
Editore: IFIP/IEEE
DOI: 10.5281/zenodo.4023242

abstractPIM: Bridging the Gap Between PIM Technology and ISA

Autori: Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatnsky
Pubblicato in: 2020
Editore: IFIP/IEEE
DOI: 10.5281/zenodo.4023246

Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory

Autori: Ben Perach, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IEEE International System-on-Chip Conference (SOCC), 2023, ISBN 979-8-3503-0011-6
Editore: IEEE
DOI: 10.1109/socc58585.2023.10256706

HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory

Autori: Batel Oved; Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky
Pubblicato in: International Conference on Modern Circuits and Systems Technologies (MOCAST), 2022, ISBN 978-1-6654-6717-9
Editore: IEEE
DOI: 10.1109/mocast54814.2022.9837685

Book chapters (1)

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory

Autori: Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IFIP Advances in Information and Communication Technology, 2021, Pagina/e 343-361, ISBN 978-3-030-81641-4
Editore: Springer, Cham
DOI: 10.1007/978-3-030-81641-4_16

Peer reviewed articles (21)

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

Autori: Rotem Ben-Hur; Ronny Ronen; Ameer Haj-Ali; Debjyoti Bhattacharjee; Adi Eliahu; Natan Peled; Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numero 1, 2019, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.36227/techrxiv.12894899

AritPIM: High-Throughput In-Memory Arithmetic

Autori: Orian Leitersdorf; Dean Leitersdorf; Jonathan Gal; Mor Dahan; Ronny Ronen; Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Emerging Topics in Computing (TETC), 2023, ISSN 2168-6750
Editore: IEEE Computer Society
DOI: 10.1109/tetc.2023.3268137

Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices

Autori: Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
Pubblicato in: Advanced Intelligent Systems, 2022, ISSN 2640-4567
Editore: Wiley-VCH GmbH
DOI: 10.1002/aisy.202100249

C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory

Autori: Mor M. Dahan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Circuits and Systems I: Regular Papers, Numero Vol. 69, No. 4, 2022, Pagina/e pp. 1595-1605, ISSN 1549-8328
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2021.3139736

Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R OxRAM Valence Change Mechanism Memristors

Autori: Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean Francois Nodin, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, ISSN 1558-3791
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsii.2023.3302235

A memristive deep belief neural network based on silicon synapses

Autori: Wei Wang, Loai Danial, Yang Li, Eric Herbelin, Evgeny Pikhay, Yakov Roizin, Barak Hoffer, Zhongrui Wang, Shahar Kvatinsky
Pubblicato in: Nature Electronics, 2022, ISSN 2520-1131
Editore: Nature Electronics (Nat Electron)
DOI: 10.1038/s41928-022-00878-9

Physical based compact model of Y-Flash memristor for neuromorphic computation

Autori: Wei Wang, Loai Danial, Eric Herbelin, Barak Hoffer, Batel Oved, Tzofnat Greenberg-Toledo, Evgeny Pikhay, Yakov Roizin, and Shahar Kvatinsky.
Pubblicato in: Applied Physics Letters, Numero Vol. 119, No. 26, 2021, ISSN 1077-3118
Editore: Applied Physics Letters
DOI: 10.1063/5.0069116

FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication

Autori: Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: Memories - Materials, Devices, Circuits and Systems, 2023, ISSN 2773-0646
Editore: Elsevier
DOI: 10.1016/j.memori.2023.100034

Training of Quantized Deep Neural Networks using a Magnetic Tunnel Junction-Based Synapse

Autori: Tzofnat Greenberg-Toledo, Ben Perach, Itay Hubara, Daniel Soudry and Shahar Kvatinsky
Pubblicato in: Semiconductor Science and Technology, 2021, Pagina/e Vol. 36, No. 11, ISSN 0268-1242
Editore: Institute of Physics Publishing
DOI: 10.1088/1361-6641/ac251b

Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Autori: Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Emerging Topics in Computing, 2023, ISSN 2168-6750
Editore: IEEE Computer Society
DOI: 10.1109/tetc.2023.3315189

IMAGING-In-Memory AlGorithms for Image processiNG

Autori: Ameer Haj-Ali, Rotem Ben-Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, Pagina/e 1-14, ISSN 1549-8328
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCSI.2018.2846699

Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing

Autori: Ameer Haj-Ali, Rotem Ben-Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IEEE Micro, Numero 38/5, 2018, Pagina/e 13-21, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2018.053631137

An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ

Autori: Ben Perach, shahar kvatinsky
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numero 27/11, 2019, Pagina/e 2473-2484, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2019.2927816

Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic

Autori: Nimrod Wald, Shahar Kvatinsky
Pubblicato in: Microelectronics Journal, Numero 86, 2019, Pagina/e 22-33, ISSN 0026-2692
Editore: Mackintosh Publications
DOI: 10.1016/j.mejo.2019.02.013

Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse

Autori: Tzofnat Greenberg-Toledo, Roee Mazor, Ameer Haj-Ali, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Circuits and Systems I: Regular Papers, Numero 66/4, 2019, Pagina/e 1571-1583, ISSN 1549-8328
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2018.2888538

CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM

Autori: Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IEEE Micro, Numero 39/1, 2019, Pagina/e 33-43, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2018.2890033

Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM)

Autori: Barak Hoffer, Vikas Rana, Stephan Menzel, Rainer Waser, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Electron Devices, Numero 67/8, 2020, Pagina/e 3115-3122, ISSN 0018-9383
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3001247

MultPIM: Fast Stateful Multiplication for Processing-in-Memory

Autori: Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Circuits and Systems II: Express Briefs, Numero Vol. 69, No. 3, pp. 1647-1651, 2022, Pagina/e 1647-1651, ISSN 1549-7747
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsii.2021.3118215

The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems

Autori: Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
Pubblicato in: ACM Journal on Emerging Technologies in Computing Systems, Numero Vol. 18, No. 2, Article No. 43, pp. 1-29, 2022, ISSN 1550-4832
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3465371

ClaPIM: Scalable Sequence Classification Using Processing-in-Memory

Autori: Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2023.3293038

Stateful Logic Using Phase Change Memory

Autori: Barak Hoffer, Nicolás Wainstein, Christopher M. Neumann, Eric Pop, Eilam Yalon, Shahar Kvatinsky
Pubblicato in: IEEE Journal of Exploratory Solid-State Computational Devices and Circuits Transactions on Electronic Devices, 2022, Pagina/e Vol. 8, No. 2, pp. 77-83, ISSN 2329-9231
Editore: IEEE
DOI: 10.1109/jxcdc.2022.3219731

Other (1)

The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm

Autori: Korgaonkar, Kunal; Ronen, Ronny; Chattopadhyay, Anupam; Kvatinsky, Shahar
Pubblicato in: Numero 1, 2019
Editore: ArXiv
DOI: 10.48550/arxiv.1910.10234