Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures

Project Information

ECHO

Grant agreement ID: 819134

DOI

10.3030/819134

EC signature date 17 January 2019

Start date 1 September 2019

End date 31 January 2026

Funded under

• EXCELLENT SCIENCE - European Research Council (ERC)

Total cost

€ 1 999 955,00

EU contribution

€ 1 999 955,00

Coordinated by

UNIVERSIDAD DE MURCIA
Spain

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Publications

Conference proceedings (21)

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory

Author(s): Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
Published in: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2022, Page(s) 157--164, ISBN 978-1-6654-6958-6
Publisher: IEEE Computer Society
DOI: 10.1109/pdp55904.2022

Rebasing Microarchitectural Research with Industry Traces

Author(s): Josué Feliu, Arthur Perais, Daniel Jimenez, Alberto Ros
Published in: International Symposium on Workload Characterization (IISWC), Issue 2023, 2023, Page(s) 100--114, ISBN 979-8-3503-0317-9
Publisher: IEEE
DOI: 10.1109/iiswc59245.2023.00027

ITSLF: Inter-Thread Store-to-Load Forwarding in Simultaneous Multithreading

Author(s): Josué Feliú, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
Published in: International Symposium on Microarchitecture (MICRO), Issue 54th, 2021, Page(s) 1296-1308, ISBN 978-1-4503-8557-2
Publisher: IEEE/ACM
DOI: 10.1145/3466752.3480086

BL∪E: A Timely, IP-based Data Prefetcher

Author(s): Alberto Ros
Published in: The 1st ML-Based Data Prefetching Competition. ML for Computer Architecture and Systems, Issue 1st, 2021, Page(s) 4
Publisher: Google

MBPlib: Modular Branch Prediction Library

Author(s): Emilio Dominguez-Sanchez, Alberto Ros
Published in: International Symposium on Performance Analysis of Systems and Software (ISPASS), Issue 2023, 2023, Page(s) 71--80, ISBN 979-8-3503-9739-0
Publisher: IEEE Computer Society
DOI: 10.1109/ispass57527.2023.00016

A Cost-Effective Entangling Prefetcher for Instructions

Author(s): Alberto Ros, Alexandra Jimborean
Published in: International Symposium on Computer Architecture (ISCA), Issue 48th, 2021, Page(s) 99-111, ISBN 978-1-6654-3333-4
Publisher: ACM
DOI: 10.1109/isca52012.2021.00017

Regional Out-of-Order Writes in Total Store Order

Author(s): Sawan Singh, Alexandra Jimborean, Alberto Ros
Published in: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, 2020, Page(s) 205-216, ISBN 9781450380751
Publisher: ACM
DOI: 10.1145/3410463.3414645

Boosting Store Buffer Efficiency with Store-Prefetch Bursts

Author(s): Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
Published in: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, Page(s) 568-580, ISBN 978-1-7281-7383-2
Publisher: IEEE
DOI: 10.1109/micro50266.2020.00054

Splash-4: Improving Scalability with Lock-Free Constructs

Author(s): Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros
Published in: International Symposium on Performance Analysis of Systems and Software (ISPASS),, Issue 2021, 2021, Page(s) 235-236, ISBN 978-1-7281-8643-6
Publisher: IEEE
DOI: 10.1109/ispass51385.2021.00044

Berti: An Accurate Local-Delta Data Prefetcher

Author(s): Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, V. Viñals-Yúfera, Alberto Ros
Published in: International Symposium on Microarchitecture (MICRO), 2022, Page(s) 975--991, ISBN 978-1-6654-6272-3
Publisher: ACM/IEEE
DOI: 10.1109/micro56248.2022.00072

Free Atomics: Hardware Atomic Operations without Fences

Author(s): Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros
Published in: International Symposium on Computer Architecture (ISCA), 2022, Page(s) 14--26, ISBN 978-1-4503-8610-4
Publisher: ACM
DOI: 10.1145/3470496.3527385

Exploring Instruction Fusion Opportunities in General Purpose Processors

Author(s): Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
Published in: Exploring Instruction Fusion Opportunities in General Purpose Processors, 2022, Page(s) 199--212, ISBN 978-1-6654-6272-3
Publisher: ACM/IEEE
DOI: 10.1109/micro56248.2022.00026

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

Author(s): Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros
Published in: International Conference on Parallel Architectures and Compilation Techniques (PACT), Issue 32nd, 2023, Page(s) 1--13, ISBN 979-8-3503-4254-3
Publisher: IEEE
DOI: 10.1109/pact58117.2023.00009

Composite Instruction Prefetching: Combining Complementary Instruction Prefetchers

Author(s): Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul Gratz, Daniel Jimenez, Samira Mirbagher-Ajorpaz
Published in: IEEE International Conference on Computer Design (ICCD), Issue 40th, 2022, Page(s) 471--478, ISBN 978-1-6654-6187-0
Publisher: IEEE Computer Society
DOI: 10.1109/iccd56317.2022.00076

Speculative Enforcement of Store Atomicity

Author(s): Alberto Ros, Stefanos Kaxiras
Published in: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, Page(s) 555-567, ISBN 978-1-7281-7383-2
Publisher: IEEE
DOI: 10.1109/micro50266.2020.00053

Splash-4: A Modern Benchmark Suite with Lock-Free Constructs

Author(s): Eduardo José Gómez-Hernández, Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros
Published in: International Symposium on Workload Characterization (IISWC), Issue 2022, 2022, Page(s) 51--64, ISBN 978-1-6654-8799-3
Publisher: IEEE Computer Society
DOI: 10.1109/iiswc55918.2022.00015

Effective Context-Sensitive Memory Dependence Prediction

Author(s): Sebastian S. Kim, Alberto Ros
Published in: Symposium on High Performance Computer Architecture (HPCA), Issue 30th, 2024, Page(s) 515--527, ISBN 979-8-3503-9314-9
Publisher: IEEE
DOI: 10.1109/hpca57654.2024.00045

Clearing the Shadows - Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design

Author(s): Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean
Published in: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, 2020, Page(s) 241-254, ISBN 9781450380751
Publisher: ACM
DOI: 10.1145/3410463.3414640

Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations

Author(s): Eduardo José Gómez-Hernández, Rubén Titos-Gil, Juan Manuel Cebrián, Stefanos Kaxiras, Alberto Ros
Published in: International Symposium on Microarchitecture (MICRO), Issue 54th, 2021, Page(s) 337-349, ISBN 978-1-4503-8557-2
Publisher: IEEE/ACM
DOI: 10.1145/3466752.3480073

TSOPER: Efficient Coherence-Based Strict Persistency

Author(s): Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras
Published in: Symposium on High Performance Computer Architecture (HPCA), Issue 27th, 2021, Page(s) 125-138, ISBN 978-1-6654-4670-9
Publisher: IEEE
DOI: 10.1109/hpca51647.2021.00021

The Entangling Instruction Prefetcher

Author(s): Alberto Ros, Alexandra Jimborean
Published in: The 1st Instruction Prefetching Championship (IPC-1), 2020, Page(s) 4
Publisher: NC State University

Peer reviewed articles (7)

On the Interactions between ILP and TLP with Hardware Transactional Memory

Author(s): Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
Published in: Microprocessors and Microsystems (MICPRO), Issue 104, 2024, Page(s) 104975, ISSN 0141-9331
Publisher: Elsevier BV
DOI: 10.1016/j.micpro.2023.104975

Alberto Ros, Alexandra Jimborean

Author(s): Wrong-Path-Aware Entangling Instruction Prefetcher
Published in: IEEE Transactions on Computers (TC), Issue 73 (2), 2024, Page(s) 548--559, ISSN 0018-9340
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2023.3337308

Speculative Inter-Thread Store-to-Load Forwarding in SMT Architectures

Author(s): Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
Published in: Journal of Parallel Distributed Computing (JPDC), Issue 173, 2023, Page(s) 94--106, ISSN 0743-7315
Publisher: Academic Press
DOI: 10.1016/j.jpdc.2022.11.007

Compiler-Assisted Compaction/Restoration of SIMD Instructions

Author(s): Juan Manuel Cebrian, Thibaud Balem, Adrian Barredo, Marc Casas, Miquel Moreto, Alberto Ros, Alexandra Jimborean
Published in: IEEE Transactions on Parallel and Distributed Systems (TPDS), Issue 33 (4), 2022, Page(s) 779-791, ISSN 1045-9219
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2021.3091015

The Entangling Instruction Prefetcher

Author(s): Alberto Ros, Alexandra Jimborean
Published in: IEEE Computer Architecture Letters, Issue 19/2, 2020, Page(s) 84-87, ISSN 1556-6056
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/lca.2020.3002947

DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory

Author(s): Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
Published in: IEEE Transactions on Parallel and Distributed Systems (TPDS), Issue 33 (1), 2022, Page(s) 1--13, ISSN 1045-9219
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2021.3085210

Analysing Software Prefetching Opportunities in Hardware Transactional Memory

Author(s): Marina Shimchenko, Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
Published in: Journal of Supercomputing (SUPE), Issue 78, 2022, Page(s) 919–944, ISSN 0920-8542
Publisher: Kluwer Academic Publishers
DOI: 10.1007/s11227-021-03897-z

Intellectual Property Rights

Patent (1)

SYSTEM AND METHOD FOR PREFETCHING BURSTS ACCESSES TO CONTIGUOUS MEMORY LOCATIONS

Application/Publication number: 20 382900
Date: 2020-10-13
Applicant(s): UNIVERSIDAD DE MURCIA