Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures

Informazioni relative al progetto

ECHO

ID dell’accordo di sovvenzione: 819134

DOI 10.3030/819134

Data della firma CE 17 Gennaio 2019

Data di avvio 1 Settembre 2019

Data di completamento 31 Gennaio 2026

Finanziato da

• EXCELLENT SCIENCE - European Research Council (ERC)

Costo totale € 1 999 955,00

Contributo UE € 1 999 955,00

Coordinato da

UNIVERSIDAD DE MURCIA
Spain

Pubblicazioni

Conference proceedings (21)

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory

Autori: Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
Pubblicato in: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2022, Pagina/e 157--164, ISBN 978-1-6654-6958-6
Editore: IEEE Computer Society
DOI: 10.1109/pdp55904.2022

Rebasing Microarchitectural Research with Industry Traces

Autori: Josué Feliu, Arthur Perais, Daniel Jimenez, Alberto Ros
Pubblicato in: International Symposium on Workload Characterization (IISWC), Numero 2023, 2023, Pagina/e 100--114, ISBN 979-8-3503-0317-9
Editore: IEEE
DOI: 10.1109/iiswc59245.2023.00027

ITSLF: Inter-Thread Store-to-Load Forwarding in Simultaneous Multithreading

Autori: Josué Feliú, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
Pubblicato in: International Symposium on Microarchitecture (MICRO), Numero 54th, 2021, Pagina/e 1296-1308, ISBN 978-1-4503-8557-2
Editore: IEEE/ACM
DOI: 10.1145/3466752.3480086

BL∪E: A Timely, IP-based Data Prefetcher

Autori: Alberto Ros
Pubblicato in: The 1st ML-Based Data Prefetching Competition. ML for Computer Architecture and Systems, Numero 1st, 2021, Pagina/e 4
Editore: Google

MBPlib: Modular Branch Prediction Library

Autori: Emilio Dominguez-Sanchez, Alberto Ros
Pubblicato in: International Symposium on Performance Analysis of Systems and Software (ISPASS), Numero 2023, 2023, Pagina/e 71--80, ISBN 979-8-3503-9739-0
Editore: IEEE Computer Society
DOI: 10.1109/ispass57527.2023.00016

A Cost-Effective Entangling Prefetcher for Instructions

Autori: Alberto Ros, Alexandra Jimborean
Pubblicato in: International Symposium on Computer Architecture (ISCA), Numero 48th, 2021, Pagina/e 99-111, ISBN 978-1-6654-3333-4
Editore: ACM
DOI: 10.1109/isca52012.2021.00017

Regional Out-of-Order Writes in Total Store Order

Autori: Sawan Singh, Alexandra Jimborean, Alberto Ros
Pubblicato in: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, 2020, Pagina/e 205-216, ISBN 9781450380751
Editore: ACM
DOI: 10.1145/3410463.3414645

Boosting Store Buffer Efficiency with Store-Prefetch Bursts

Autori: Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
Pubblicato in: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, Pagina/e 568-580, ISBN 978-1-7281-7383-2
Editore: IEEE
DOI: 10.1109/micro50266.2020.00054

Splash-4: Improving Scalability with Lock-Free Constructs

Autori: Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros
Pubblicato in: International Symposium on Performance Analysis of Systems and Software (ISPASS),, Numero 2021, 2021, Pagina/e 235-236, ISBN 978-1-7281-8643-6
Editore: IEEE
DOI: 10.1109/ispass51385.2021.00044

Berti: An Accurate Local-Delta Data Prefetcher

Autori: Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, V. Viñals-Yúfera, Alberto Ros
Pubblicato in: International Symposium on Microarchitecture (MICRO), 2022, Pagina/e 975--991, ISBN 978-1-6654-6272-3
Editore: ACM/IEEE
DOI: 10.1109/micro56248.2022.00072

Free Atomics: Hardware Atomic Operations without Fences

Autori: Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros
Pubblicato in: International Symposium on Computer Architecture (ISCA), 2022, Pagina/e 14--26, ISBN 978-1-4503-8610-4
Editore: ACM
DOI: 10.1145/3470496.3527385

Exploring Instruction Fusion Opportunities in General Purpose Processors

Autori: Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
Pubblicato in: Exploring Instruction Fusion Opportunities in General Purpose Processors, 2022, Pagina/e 199--212, ISBN 978-1-6654-6272-3
Editore: ACM/IEEE
DOI: 10.1109/micro56248.2022.00026

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

Autori: Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros
Pubblicato in: International Conference on Parallel Architectures and Compilation Techniques (PACT), Numero 32nd, 2023, Pagina/e 1--13, ISBN 979-8-3503-4254-3
Editore: IEEE
DOI: 10.1109/pact58117.2023.00009

Composite Instruction Prefetching: Combining Complementary Instruction Prefetchers

Autori: Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul Gratz, Daniel Jimenez, Samira Mirbagher-Ajorpaz
Pubblicato in: IEEE International Conference on Computer Design (ICCD), Numero 40th, 2022, Pagina/e 471--478, ISBN 978-1-6654-6187-0
Editore: IEEE Computer Society
DOI: 10.1109/iccd56317.2022.00076

Speculative Enforcement of Store Atomicity

Autori: Alberto Ros, Stefanos Kaxiras
Pubblicato in: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, Pagina/e 555-567, ISBN 978-1-7281-7383-2
Editore: IEEE
DOI: 10.1109/micro50266.2020.00053

Splash-4: A Modern Benchmark Suite with Lock-Free Constructs

Autori: Eduardo José Gómez-Hernández, Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros
Pubblicato in: International Symposium on Workload Characterization (IISWC), Numero 2022, 2022, Pagina/e 51--64, ISBN 978-1-6654-8799-3
Editore: IEEE Computer Society
DOI: 10.1109/iiswc55918.2022.00015

Effective Context-Sensitive Memory Dependence Prediction

Autori: Sebastian S. Kim, Alberto Ros
Pubblicato in: Symposium on High Performance Computer Architecture (HPCA), Numero 30th, 2024, Pagina/e 515--527, ISBN 979-8-3503-9314-9
Editore: IEEE
DOI: 10.1109/hpca57654.2024.00045

Clearing the Shadows - Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design

Autori: Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean
Pubblicato in: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, 2020, Pagina/e 241-254, ISBN 9781450380751
Editore: ACM
DOI: 10.1145/3410463.3414640

Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations

Autori: Eduardo José Gómez-Hernández, Rubén Titos-Gil, Juan Manuel Cebrián, Stefanos Kaxiras, Alberto Ros
Pubblicato in: International Symposium on Microarchitecture (MICRO), Numero 54th, 2021, Pagina/e 337-349, ISBN 978-1-4503-8557-2
Editore: IEEE/ACM
DOI: 10.1145/3466752.3480073

TSOPER: Efficient Coherence-Based Strict Persistency

Autori: Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras
Pubblicato in: Symposium on High Performance Computer Architecture (HPCA), Numero 27th, 2021, Pagina/e 125-138, ISBN 978-1-6654-4670-9
Editore: IEEE
DOI: 10.1109/hpca51647.2021.00021

The Entangling Instruction Prefetcher

Autori: Alberto Ros, Alexandra Jimborean
Pubblicato in: The 1st Instruction Prefetching Championship (IPC-1), 2020, Pagina/e 4
Editore: NC State University

Peer reviewed articles (7)

On the Interactions between ILP and TLP with Hardware Transactional Memory

Autori: Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
Pubblicato in: Microprocessors and Microsystems (MICPRO), Numero 104, 2024, Pagina/e 104975, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2023.104975

Alberto Ros, Alexandra Jimborean

Autori: Wrong-Path-Aware Entangling Instruction Prefetcher
Pubblicato in: IEEE Transactions on Computers (TC), Numero 73 (2), 2024, Pagina/e 548--559, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2023.3337308

Speculative Inter-Thread Store-to-Load Forwarding in SMT Architectures

Autori: Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
Pubblicato in: Journal of Parallel Distributed Computing (JPDC), Numero 173, 2023, Pagina/e 94--106, ISSN 0743-7315
Editore: Academic Press
DOI: 10.1016/j.jpdc.2022.11.007

Compiler-Assisted Compaction/Restoration of SIMD Instructions

Autori: Juan Manuel Cebrian, Thibaud Balem, Adrian Barredo, Marc Casas, Miquel Moreto, Alberto Ros, Alexandra Jimborean
Pubblicato in: IEEE Transactions on Parallel and Distributed Systems (TPDS), Numero 33 (4), 2022, Pagina/e 779-791, ISSN 1045-9219
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2021.3091015

The Entangling Instruction Prefetcher

Autori: Alberto Ros, Alexandra Jimborean
Pubblicato in: IEEE Computer Architecture Letters, Numero 19/2, 2020, Pagina/e 84-87, ISSN 1556-6056
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/lca.2020.3002947

DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory

Autori: Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
Pubblicato in: IEEE Transactions on Parallel and Distributed Systems (TPDS), Numero 33 (1), 2022, Pagina/e 1--13, ISSN 1045-9219
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2021.3085210

Analysing Software Prefetching Opportunities in Hardware Transactional Memory

Autori: Marina Shimchenko, Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
Pubblicato in: Journal of Supercomputing (SUPE), Numero 78, 2022, Pagina/e 919–944, ISSN 0920-8542
Editore: Kluwer Academic Publishers
DOI: 10.1007/s11227-021-03897-z

Diritti di proprietà intellettuale

Patent (1)

SYSTEM AND METHOD FOR PREFETCHING BURSTS ACCESSES TO CONTIGUOUS MEMORY LOCATIONS

Numero candidatura/pubblicazione: 20 382900
Data: 2020-10-13
Candidato/i: UNIVERSIDAD DE MURCIA