Livrables
Designed MMIC’s and packages will be scrutinized from the level of MMIC schematics, layout and simulation performance. The evaluation of simulated performance includes consideration of involved models, small-signal S parameters simulations, Harmonic balance simulations, and EM simulations of passives. The report will include bare-die performance, and a particular focus on the influence from the FOWLP. In this first run the main focus is not on reaching utmost performance of the packaged components, but to understand material system interactions to prepare for high-end performance in the second manufacturing run. The CDR Run 1 will end with the delivery of the stack of GDS files from the design, the different versions and the test patterns as well as the package details. All this material will be documented together with the output from the CDR into a written report This deliverable is also a milestone, M1
Kick-off meetingKick-off meeting to inform all partners about management and communication flows in the project.
Evaluation report run 2D 4.2 The results of in-package measurements will be presented in a document, the report will detail the best results obtained and present the rational of the choice of MMIC’s. D4.2 will also include results from on-wafer measurements of second iteration MMICs.
Report on Communication, Dissemination and Exploitation actionsThe communication, dissemination, and exploitation report will include all such related activities that have been carried out in the project.
Plan for Communication, Dissemination and Exploitation of project resultsThe communication plan will contain the plan of communication activities, a plan for dissemination of project results and a plan for exploitation of project results and handling of IP rights linked to project outputs
Evaluation report run 11 The results of on-wafer measurements of Run 1 MMIC will be presented in a document. The report will also contain the rational of the choice of the MMIC’s for packaging.
CDR Run 2 ReportDesigned MMIC’s and packages will be scrutinized from the level of MMIC schematics, layout and simulation performance. The evaluation of simulated performance includes consideration of involved models, small-signal S parameters simulations, Harmonic balance simulations, and EM simulations of passives. In this second run the main focus is to optimize the MMICs for best possible performance, firstly as bare dies but also the possibility to compensate influence from package. The CDR Run 2 will end with the delivery of the stack of GDS files from the design, the different versions and the test patterns as well as the package details. All this material will be documented together with the output from the CDR into a written report.
Package test structures prepared with solder bumps, e.g., 50 ohm through line will be attached to alumina PCBs.
Delivery of wafers carrying SS and PA MMICsThe wafers manufactured using the mask-sets based on MMIC designs from MC2 and CHALMERS will be made available to the partners of the projects. Wafers will be submitted to on-wafer testings and then diced. Some chips will be kept for bare-die characterization and other MMIC’s will be sent to Fraunhofer for packaging. Tracability will be kept between MMICs version and between Run 1 and Run 2 of manufacturing
Delivery of FOWLPs and test structuresThe MMICs manufactured by OMMIC will be encapsulated into FOWLPs and sent back for characterization to Chalmers and OMMIC-MC2
The data management plan should include information on: *The handling of research data during and after the end of the project *What data will be collected, processed and/or generated *Which methodology & standards will be applied *Whether data will be shared/made open access and *How data will be curated and preserved (including after the end of the project).
Publications
Auteurs:
Thanh Ngoc Thi Do, Yu Yan, Dan Kuylenstierna
Publié dans:
2020 IEEE Asia-Pacific Microwave Conference (APMC), 2020, Page(s) 113-115, ISBN 978-1-7281-6962-0
Éditeur:
IEEE
DOI:
10.1109/apmc47863.2020.9331430
Auteurs:
Yu Yan, Thanh Ngoc Thi Do, Dan Kuylenstierna
Publié dans:
2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2020, Page(s) 1-3, ISBN 978-1-7281-9749-4
Éditeur:
IEEE
DOI:
10.1109/bcicts48439.2020.9392981
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