The design phase started with the user requirements for future space applications and the translation to block level technical performance parameters. The output of requirement phase has allowed to start the actual design of all digital (computing, data processing) and analog blocks (data collection & transmission) that will form the radiation hardened platform. After the feasibility studies and architectural trade-offs following IP library components have been designed, simulations on circuit level were executed to verify the functionality in all operating conditions, followed by TCAD radiation simulations to confirm that the designs are hardened against radiation effects.
Digital Core gates, 1.8V IO modules, Back Bias Generator (BBG), TID Sensor, Stub Series Terminated Logic (SSTL) modules, PLL clock generator, ADC, DAC, SERDES TX.
The design phase is supported by physics-based simulations of interactions between radiation and the silicon devices. This generates a circuit level simulation model of the critical charge collection caused by an incident particle e.g. heavy ion or proton. Extensive charge injection simulations indicate where the weaker nodes in a circuit are located and allows to implement circuit-level mitigation techniques. A set of design hardening rules are defined to mitigate the long-term drift effects caused by radiation, as well as to cope with instantaneous charge collection effects caused by charged particles.
In parallel, feasibility and in-depth trade-off studies have been performed to find a suitable standard package and CPGA 256 was selected for the test vehicle.
A digital test vehicle (DTV) containing the following IPs have been taped out, manufactured, and packaged. 100 dies were produced in total and made ready for electrical characterization and TID/SEE radiation campaigns.
Digital Core gates, IO modules, Back Bias Generator (BBG), TID Sensor, Stub Series Terminated Logic (SSTL) modules, PLL clock generator, Oscillator, Power Management Unit, IV Reference, LVDS.
Extra test structures for radiation measurements are added to the digital test vehicle by IMEC.
For electrical characterization, a load test board and an adapter board are designed, developed, and manufactured. To test the PLL jitter, which requires a special sensitive setup, a PLL Jitter test board is designed, developed, and manufactured. ESD tests are executed in IMEC premises.
Test plan for Digital Test Vehicle is developed. Detailed documentation about which feature to test, what the expected results are, and the test configurations are generated.
For commercial usage, the Digital IPs and the PLL are packaged with user & integration guides, multiple EDA views and associated documentations
