Periodic Reporting for period 2 - EFESOS (Evaluation of 22 nm Fully-depleted Silicon-on-insulator technology for Space)
Periodo di rendicontazione: 2021-09-01 al 2022-11-30
The EFESOS project aims to develop and evaluate a fully European microelectronics design flow based on the commercially available 22FDX process from Global Foundries, in Dresden (Germany). A complete electrical, environmental and reliability validation of the technology will be performed, and the resulting design flow will be evaluated according to the European space standards.
The EFESOS IP platform will enable many new applications that today are not yet possible with the available technology and will make Europe stronger and more independent in the field of space microelectronics. EFESOS will:
- Provide the European space market players and start-ups with affordable and independent access to a proven high-reliable design platform for their rad-hard application specific chip and standard product designs, reducing dependency on export-restricted technologies that are of strategic importance to future European space efforts and open new competition opportunities.
- Provide the space market players and start-ups with knowledge and know-how in the field of rad-hard chip design, which enhances the technical capabilities and overall competitiveness of the European space industry vendors on the global market.
- Improve the European scientific level in development of radiation-hardened electronics for space and non-space applications. Measuring the radiation behavior of the 22FDX process technology is already a contribution to the scientific knowledge database.
- Stimulate European development of radiation-hardened electronics at newest, advanced high-performance technology nodes. The EFESOS project results will provide the opportunity of creating space components in the Global Foundries 22nm FD-SOI process node compared to today’s commonly used 28-65nm nodes.
The EFESOS activity has produced the following radhard IPs:
- An extensive set of digital standard cells with 3 different transistor gate lengths and 4 distinct threshold voltage flavors, resulting in 12 variants of each digital standard cell which allows design optimization towards speed, power, area and reliability
- A set of general-purpose input/output cells to interface digital and analog signals between the chip core and chip package
- A set of high-speed input/output cells to allow up to 1.6 Gbps data communication
- A back-bias generator IP which uses the 22FDX technology specific back-biasing feature to implement a compensation scheme for accumulated radiation effects in digital circuits
- A low-jitter programmable clock generation IP which incorporates many mitigation techniques to ensure correct operation of this timing critical block of the system
These IPs were integrated into a test vehicle, which was manufactured in the target technology in the foundry of GlobalFoundries in Dresden and afterwards packaged to start electrical, functional and radiation testing.
- An analog to digital converter working as a high-speed (1-2 GSPS) medium resolution (10-bit) for satellite communications applications. Besides, its high conversion rate enables communications in the L-band (1-2GHz) with direct down-conversion
- A digital to analog converter covering a range of high-speed (1-2 GSPS) and medium resolution (10-bit). For communication purposes this IP could be as an interface between the digital baseband and the high-speed analog part in the transmitter.
- A high-speed (10BGPS) serializer to allow communications between digital systems at very high speed through backplanes or cables.
Due to project timing constrains and high cost, the analog test vehicle for these IPs were descoped. In case additional funding could happen, it is expected to manufacture them in the target technology, package and carry out electrical and radiation validation.
The EFESOS IP platform will enable many new applications that today are not yet possible with the available technology and will make Europe stronger and more independent in the field of space microelectronics. EFESOS will:
- Provide the European space market players and start-ups with affordable and independent access to a proven high-reliable design platform for their rad-hard application specific chip and standard product designs, reducing dependency on export-restricted technologies that are of strategic importance to future European space efforts and open new competition opportunities.
- Provide the space market players and start-ups with knowledge and know-how in the field of rad-hard chip design, which enhances the technical capabilities and overall competitiveness of the European space industry vendors on the global market.
- Improve the European scientific level in development of radiation-hardened electronics for space and non-space applications. Measuring the radiation behavior of the 22FDX process technology is already a contribution to the scientific knowledge database.
- Stimulate European development of radiation-hardened electronics at newest, advanced high-performance technology nodes. The EFESOS project results will provide the opportunity of creating space components in the Global Foundries 22nm FD-SOI process node compared to today’s commonly used 28-65nm nodes.
The EFESOS activity has produced the following radhard IPs:
- An extensive set of digital standard cells with 3 different transistor gate lengths and 4 distinct threshold voltage flavors, resulting in 12 variants of each digital standard cell which allows design optimization towards speed, power, area and reliability
- A set of general-purpose input/output cells to interface digital and analog signals between the chip core and chip package
- A set of high-speed input/output cells to allow up to 1.6 Gbps data communication
- A back-bias generator IP which uses the 22FDX technology specific back-biasing feature to implement a compensation scheme for accumulated radiation effects in digital circuits
- A low-jitter programmable clock generation IP which incorporates many mitigation techniques to ensure correct operation of this timing critical block of the system
These IPs were integrated into a test vehicle, which was manufactured in the target technology in the foundry of GlobalFoundries in Dresden and afterwards packaged to start electrical, functional and radiation testing.
- An analog to digital converter working as a high-speed (1-2 GSPS) medium resolution (10-bit) for satellite communications applications. Besides, its high conversion rate enables communications in the L-band (1-2GHz) with direct down-conversion
- A digital to analog converter covering a range of high-speed (1-2 GSPS) and medium resolution (10-bit). For communication purposes this IP could be as an interface between the digital baseband and the high-speed analog part in the transmitter.
- A high-speed (10BGPS) serializer to allow communications between digital systems at very high speed through backplanes or cables.
Due to project timing constrains and high cost, the analog test vehicle for these IPs were descoped. In case additional funding could happen, it is expected to manufacture them in the target technology, package and carry out electrical and radiation validation.
The design phase started with the user requirements for future space applications and the translation to block level technical performance parameters. The output of requirement phase has allowed to start the actual design of all digital (computing, data processing) and analog blocks (data collection & transmission) that will form the radiation hardened platform. After the feasibility studies and architectural trade-offs following IP library components have been designed, simulations on circuit level were executed to verify the functionality in all operating conditions, followed by TCAD radiation simulations to confirm that the designs are hardened against radiation effects.
Digital Core gates, 1.8V IO modules, Back Bias Generator (BBG), TID Sensor, Stub Series Terminated Logic (SSTL) modules, PLL clock generator, ADC, DAC, SERDES TX.
The design phase is supported by physics-based simulations of interactions between radiation and the silicon devices. This generates a circuit level simulation model of the critical charge collection caused by an incident particle e.g. heavy ion or proton. Extensive charge injection simulations indicate where the weaker nodes in a circuit are located and allows to implement circuit-level mitigation techniques. A set of design hardening rules are defined to mitigate the long-term drift effects caused by radiation, as well as to cope with instantaneous charge collection effects caused by charged particles.
In parallel, feasibility and in-depth trade-off studies have been performed to find a suitable standard package and CPGA 256 was selected for the test vehicle.
A digital test vehicle (DTV) containing the following IPs have been taped out, manufactured, and packaged. 100 dies were produced in total and made ready for electrical characterization and TID/SEE radiation campaigns.
Digital Core gates, IO modules, Back Bias Generator (BBG), TID Sensor, Stub Series Terminated Logic (SSTL) modules, PLL clock generator, Oscillator, Power Management Unit, IV Reference, LVDS.
Extra test structures for radiation measurements are added to the digital test vehicle by IMEC.
For electrical characterization, a load test board and an adapter board are designed, developed, and manufactured. To test the PLL jitter, which requires a special sensitive setup, a PLL Jitter test board is designed, developed, and manufactured. ESD tests are executed in IMEC premises.
Test plan for Digital Test Vehicle is developed. Detailed documentation about which feature to test, what the expected results are, and the test configurations are generated.
For commercial usage, the Digital IPs and the PLL are packaged with user & integration guides, multiple EDA views and associated documentations
Digital Core gates, 1.8V IO modules, Back Bias Generator (BBG), TID Sensor, Stub Series Terminated Logic (SSTL) modules, PLL clock generator, ADC, DAC, SERDES TX.
The design phase is supported by physics-based simulations of interactions between radiation and the silicon devices. This generates a circuit level simulation model of the critical charge collection caused by an incident particle e.g. heavy ion or proton. Extensive charge injection simulations indicate where the weaker nodes in a circuit are located and allows to implement circuit-level mitigation techniques. A set of design hardening rules are defined to mitigate the long-term drift effects caused by radiation, as well as to cope with instantaneous charge collection effects caused by charged particles.
In parallel, feasibility and in-depth trade-off studies have been performed to find a suitable standard package and CPGA 256 was selected for the test vehicle.
A digital test vehicle (DTV) containing the following IPs have been taped out, manufactured, and packaged. 100 dies were produced in total and made ready for electrical characterization and TID/SEE radiation campaigns.
Digital Core gates, IO modules, Back Bias Generator (BBG), TID Sensor, Stub Series Terminated Logic (SSTL) modules, PLL clock generator, Oscillator, Power Management Unit, IV Reference, LVDS.
Extra test structures for radiation measurements are added to the digital test vehicle by IMEC.
For electrical characterization, a load test board and an adapter board are designed, developed, and manufactured. To test the PLL jitter, which requires a special sensitive setup, a PLL Jitter test board is designed, developed, and manufactured. ESD tests are executed in IMEC premises.
Test plan for Digital Test Vehicle is developed. Detailed documentation about which feature to test, what the expected results are, and the test configurations are generated.
For commercial usage, the Digital IPs and the PLL are packaged with user & integration guides, multiple EDA views and associated documentations
EFESOS combines advanced European chip manufacturing technology with a new European chip design platform that includes intrinsic radiation hardening for space applications. This is a unique combination that will allow faster development of space applications with more compute power, higher data through-put, while consuming less power. At the same time, it provides an ITAR-free solution to the benefit of European non-dependence