Training researchers in III-V semiconductors
CMOS is the dominant commercial process technology for the fabrication of integrated circuits. Developed in 1960, CMOS processes originally employed metal as the gate conductor. Today, the gates are made from polysilicon. There is also a shift towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. Specifically, there is growing interest in the integration of III-V materials and other complex semiconductors that have advantages over silicon. The EU-funded DESIGN-EID project will address the technological challenge by investigating the impact of defects on electronic and photonic device performance. It will train three early stage researchers to bridge the gap between predictive simulations, experimental materials and device development.
Fields of science
Call for proposal
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Funding SchemeMSCA-ITN-EID - European Industrial Doctorates
1200 Copenhagen V