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Defect Simulation and Material Growth of III-V Nanostructures- European Industrial Doctorate Program

Project description

Training researchers in III-V semiconductors

CMOS is the dominant commercial process technology for the fabrication of integrated circuits. Developed in 1960, CMOS processes originally employed metal as the gate conductor. Today, the gates are made from polysilicon. There is also a shift towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. Specifically, there is growing interest in the integration of III-V materials and other complex semiconductors that have advantages over silicon. The EU-funded DESIGN-EID project will address the technological challenge by investigating the impact of defects on electronic and photonic device performance. It will train three early stage researchers to bridge the gap between predictive simulations, experimental materials and device development.

Call for proposal

H2020-MSCA-ITN-2019
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Coordinator

UNIVERSITY OF GLASGOW
Address
University Avenue
G12 8QQ Glasgow
United Kingdom
Activity type
Higher or Secondary Education Establishments
EU contribution
€ 336 858,40

Participants (2)

IBM RESEARCH GMBH
Switzerland
EU contribution
€ 343 782,56
Address
Saeumerstrasse 4
8803 Rueschlikon
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
SYNOPSYS DENMARK APS
Denmark
EU contribution
€ 198 348
Address
Fruebjergvej 3
1200 Copenhagen V
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)