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Origami electronics for three dimensional integration of computational devices

Project description

Novel 3D stacking technology to extend Moore’s law

Moore’s law, which states that the number of transistors that can be placed inexpensively on an integrated circuit will double every 18 months, has guided transistor design for more than 50 years. However, the continuous shrink of silicon chips approaches physical limits. Novel packaging architectures such as 3D integration, the vertical chip integration, has long held promise for increasing the transistor count. The ORIGENAL project will take a radically new approach to address ultra-dense 3D integration of chips. At the core of ORIGENAL’s 3D packaging concept is a thin-film transistor technology built on a thin foil substrate. The proposed architecture allows the stacking of thousands of layers on top of each other, permitting further miniaturisation for another 30 years.


Increasing the integrated circuits complexity by lateral scaling, known as Moore’s law, was the major driving force for the semiconductor industry. Now, after more than 4 decades down scaling is approaching fundamental and also economic limitations, and new solutions for further increasing the transistor count are explored. Utilizing the third dimension in chip architecture is one of the most promising directions. However, current solutions like wafer-to-wafer stacking will only deliver solutions for the short term with maximum some tens of layers on-top of each other’s.
In the ORIGENAL project we propose a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices by using a thin-film-transistor (TFT) technology on thin foil substrate and the subsequent topological folding in order to achieve a dense 3D packaging with completely new integration architectures. This radically new approach will enable the stacking of thousands of layers on top of each other’s, each containing state-of-the-art CMOS circuits and thus will provide enough fuel to further increase the transistor count on a chip according to Moore’s law for more than 30 years. In addition, new computing concepts like neuromorphic computing will significantly benefit from the highly interconnected architecture developed in this project.
The proposal focuses on the development of a suitable thin-film-transistor technology on ultrathin-foil, the 3D interconnect and architecture, and the required technology for high precision folding. Achieving the ambitious objectives requires an interdisciplinary approach including contributions from Material science, electrical engineering, mechanical engineering, biology, physics and chemistry.
The proposed forefront research will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.

Call for proposal


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Net EU contribution
€ 334 132,50
Gauss-strasse 20
42119 Wuppertal

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Nordrhein-Westfalen Düsseldorf Wuppertal, Kreisfreie Stadt
Activity type
Higher or Secondary Education Establishments
Other funding
€ 0,00

Participants (4)