Project description
Novel 3D stacking technology to extend Moore’s law
Moore’s law, which states that the number of transistors that can be placed inexpensively on an integrated circuit will double every 18 months, has guided transistor design for more than 50 years. However, the continuous shrink of silicon chips approaches physical limits. Novel packaging architectures such as 3D integration, the vertical chip integration, has long held promise for increasing the transistor count. The ORIGENAL project will take a radically new approach to address ultra-dense 3D integration of chips. At the core of ORIGENAL’s 3D packaging concept is a thin-film transistor technology built on a thin foil substrate. The proposed architecture allows the stacking of thousands of layers on top of each other, permitting further miniaturisation for another 30 years.
Fields of science
- engineering and technologymechanical engineering
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectrical engineering
- engineering and technologyenvironmental engineeringenergy and fuels
- social scienceslaw
Programme(s)
Funding Scheme
RIA - Research and Innovation actionCoordinator
42119 Wuppertal
Germany
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Participants (4)
02150 Espoo
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56126 Pisa
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1040 Wien
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52074 Aachen
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The organization defined itself as SME (small and medium-sized enterprise) at the time the Grant Agreement was signed.