Descripción del proyecto
Una nueva tecnología de apilamiento tridimensional para ampliar la ley de Moore
La ley de Moore —que afirma que el número de transistores que se puede colocar de manera asequible en un circuito integrado se doblará cada dieciocho meses— ha sido la base del diseño de transistores durante más de cincuenta años. Sin embargo, los chips de silicio son cada vez más pequeños y se están acercando a los límites físicos. Las nuevas arquitecturas de encapsulado, como la integración tridimensional —la integración vertical de chips— se han presentado desde hace tiempo como la solución para el aumento en el número de transistores. El proyecto ORIGENAL abordará la integración tridimensional ultradensa de chips desde una filosofía radicalmente nueva. Su fundamento de encapsulado consiste en una tecnología de transistores de película fina integrados en un delgado sustrato sobre láminas. La arquitectura propuesta permite el apilamiento de miles de capas, lo que facilitará una mayor miniaturización durante los próximos treinta años.
Objetivo
Increasing the integrated circuits complexity by lateral scaling, known as Moore’s law, was the major driving force for the semiconductor industry. Now, after more than 4 decades down scaling is approaching fundamental and also economic limitations, and new solutions for further increasing the transistor count are explored. Utilizing the third dimension in chip architecture is one of the most promising directions. However, current solutions like wafer-to-wafer stacking will only deliver solutions for the short term with maximum some tens of layers on-top of each other’s.
In the ORIGENAL project we propose a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices by using a thin-film-transistor (TFT) technology on thin foil substrate and the subsequent topological folding in order to achieve a dense 3D packaging with completely new integration architectures. This radically new approach will enable the stacking of thousands of layers on top of each other’s, each containing state-of-the-art CMOS circuits and thus will provide enough fuel to further increase the transistor count on a chip according to Moore’s law for more than 30 years. In addition, new computing concepts like neuromorphic computing will significantly benefit from the highly interconnected architecture developed in this project.
The proposal focuses on the development of a suitable thin-film-transistor technology on ultrathin-foil, the 3D interconnect and architecture, and the required technology for high precision folding. Achieving the ambitious objectives requires an interdisciplinary approach including contributions from Material science, electrical engineering, mechanical engineering, biology, physics and chemistry.
The proposed forefront research will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.
Ámbito científico
- engineering and technologymechanical engineering
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectrical engineering
- engineering and technologyenvironmental engineeringenergy and fuels
- social scienceslaw
Palabras clave
Programa(s)
Convocatoria de propuestas
Consulte otros proyectos de esta convocatoriaConvocatoria de subcontratación
H2020-FETOPEN-2018-2019-2020-01
Régimen de financiación
RIA - Research and Innovation actionCoordinador
42119 Wuppertal
Alemania