Descripción del proyecto
Nuevo plano de comunicación inalámbrica integrado en chips
Las plataformas informáticas y los sistemas de comunicación inalámbricos del futuro requieren velocidades de transmisión de datos mucho más elevadas, una mayor flexibilidad y una eficacia energética considerablemente más alta que en los sistemas actuales. Ahora que los procesadores heterogéneos están disponibles de forma generalizada, se necesitan nuevas plataformas para aprovechar una enorme potencia de computación. Para garantizar la eficacia de los cuasi ASIC (circuitos integrados para aplicaciones específicas) sin el coste, el tiempo de desarrollo o las limitaciones, el proyecto financiado con fondos europeos WiPLASH está desarrollando un plano de comunicación inalámbrica integrado en chips para disponer de la plasticidad estructural, la capacidad de reconfiguración y la adaptación a cualquier requisito de aplicaciones sin perder su carácter general. En particular, el proyecto diseñará un prototipo de antena de grafeno en miniatura y ajustable en la banda de los terahercios. Además, cointegrará componentes de radiofrecuencia de grafeno con transceptores de ondas submilimétricas y demostrará la eficacia de redes a escala de chips inalámbricos reconfigurables de bajo consumo.
Objetivo
The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability.
In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.
Ámbito científico
- engineering and technologynanotechnologynano-materialstwo-dimensional nanostructuresgraphene
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringanalogue electronics
- natural sciencescomputer and information sciencesartificial intelligencemachine learningdeep learning
- engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technology
Palabras clave
Programa(s)
Convocatoria de propuestas
Consulte otros proyectos de esta convocatoriaConvocatoria de subcontratación
H2020-FETOPEN-2018-2019-2020-01
Régimen de financiación
RIA - Research and Innovation actionCoordinador
08034 Barcelona
España