Periodic Reporting for period 2 - COMAP-4S (COmponents and MAcrocomponents Packaging For Space)
Période du rapport: 2021-09-01 au 2024-06-30
The data transmission rate has drastically increased over the last years. This trend will continue and accelerate through autonomous driving, 5G communication, and climate change. In data transfer, positioning, ecological and environmental survey, satellites are indispensable. New technological developments and business models call for more specialized and smaller satellites.
The space applications market is undergoing a substantial transformation, with new business models and an increased use of deeply integrated electronics on board satellites, for digital or analog functions. Such miniaturized equipment allows drastic reductions of the mass and finally cheaper launches per satellite.
However, despite the DSM technologies currently used for manufacturing electronic components for space, efficient and competitive packaging of large components remains a roadblock for downsizing satellites further.
Following-up innovative approaches developed in recent years, the main objective of this project is to design and qualify a macro-component demonstrator for space applications. It will offer unmatched figures of merit for the packaging of electronic components in space applications. This holds for interconnection density, die size, integration density, combined with a threefold cost reduction compared to conventional packages.
To meet this ambitious challenge, a work plan was deployed with progressive steps, in terms of complexity: die size, number of interconnections, routing density in the PCB and substrates, and power dissipation levels. Based on the complexity grades, different classes of SIP Digital, called “SIP-D”, “SIP-D extended”, “SIP-D extra” and “SIP-D Extra-addon”, were defined and used as specifications for designing and manufacturing representative Test Vehicles. After set-up of the assembly and packaging processes, incl. the design rules, and through iterations, the Test Vehicles (TVs) were submitted to test sequences according to ESCC standards. The results after evaluation and qualification of the technological bricks revealed their aptitude for building technological and functional demonstrators which integrate processing functions in a SIP:
• SIP ULTRA300 features very high density of implementation and routing in an organic and non-hermetic package, and pre-figures an innovative and “easy-to-use” solution for European designers of core processing units for Space
• SIP-D demonstrator features Flip-Chip (FC) assembly of 225mm² dies with full matrix of I/O bumps at 500µm pitch, implemented on Low CTE PCB having up to 4 levels of stacked microvias, encapsulated into an organic and non-hermetic package able to manage up to 5W power dissipation. This demonstrator passed successfully ESCC test sequences in environmental conditions representative of Space applications
COMAP-4S project demonstrates also the beginnings of a European supply chain, built around the beneficiaries within the Consortium and their 1st rank suppliers, and able to provide non-dependent solutions for SIP
The space applications market is undergoing a substantial transformation, with new business models and an increased use of deeply integrated electronics on board satellites, for digital or analog functions. Such miniaturized equipment allows drastic reductions of the mass and finally cheaper launches per satellite.
However, despite the DSM technologies currently used for manufacturing electronic components for space, efficient and competitive packaging of large components remains a roadblock for downsizing satellites further.
Following-up innovative approaches developed in recent years, the main objective of this project is to design and qualify a macro-component demonstrator for space applications. It will offer unmatched figures of merit for the packaging of electronic components in space applications. This holds for interconnection density, die size, integration density, combined with a threefold cost reduction compared to conventional packages.
To meet this ambitious challenge, a work plan was deployed with progressive steps, in terms of complexity: die size, number of interconnections, routing density in the PCB and substrates, and power dissipation levels. Based on the complexity grades, different classes of SIP Digital, called “SIP-D”, “SIP-D extended”, “SIP-D extra” and “SIP-D Extra-addon”, were defined and used as specifications for designing and manufacturing representative Test Vehicles. After set-up of the assembly and packaging processes, incl. the design rules, and through iterations, the Test Vehicles (TVs) were submitted to test sequences according to ESCC standards. The results after evaluation and qualification of the technological bricks revealed their aptitude for building technological and functional demonstrators which integrate processing functions in a SIP:
• SIP ULTRA300 features very high density of implementation and routing in an organic and non-hermetic package, and pre-figures an innovative and “easy-to-use” solution for European designers of core processing units for Space
• SIP-D demonstrator features Flip-Chip (FC) assembly of 225mm² dies with full matrix of I/O bumps at 500µm pitch, implemented on Low CTE PCB having up to 4 levels of stacked microvias, encapsulated into an organic and non-hermetic package able to manage up to 5W power dissipation. This demonstrator passed successfully ESCC test sequences in environmental conditions representative of Space applications
COMAP-4S project demonstrates also the beginnings of a European supply chain, built around the beneficiaries within the Consortium and their 1st rank suppliers, and able to provide non-dependent solutions for SIP
The work plan is structured in 3 phases for maturating, qualifying, and demonstrating the technologies, and 6 technical Work Packages, from the beginning in January 2020 until the end of COMAP-4S in June 2024.
The State-of-the-Art (SoA) and the market and supply-chain analyses confirmed COMAP-4S project is compatible with the main objectives of the relevant European space road maps. Furthermore, the requirements applicable to the technologies (HDI PCB, thermal management, and SIP & assembly technologies) were specified towards the targeted objectives.
After selecting low CTE materials suitable for the intended application, PCBs were defined and manufactured. A test plan, according to ECSS PCB qualification standard, was applied to the TVs. It resulted into success and it is stated that the PCB technology used demonstrated an unmatched reliability up to 4 levels of stacked microvias with small dimensions. Outcomes of this task surpass by a multitude the current SoA HDI PCB technology used for ESA. The results were presented at IPC APEX 2023.
Based on the packaging specification, where SIP is characterized vs its thermal dissipation level, different thermal management concepts were modelled and solutions adapted to each class were identified. First thermal TVs were assembled and calibrated in 2021. After testing, an iterative process was engaged to develop and test thermal TVs more representative of real dissipating modules. The experimental results showed the capability for molding SIP by various processes, with packages able to manage power dissipation of the embedded dies up to 5W, in agreement with the simulation results. The thermal management solution was tested and characterized also in the SIP-D demonstrator at the last phase of the project. Solutions for higher dissipation levels (metal lids or structures included in the molding) could not be fully evaluated in environmental test conditions.
During the 1st phase of the project, the FC assembly technologies (materials and processes) were evaluated according to a test sequence based on applicable ESCC specifications.
Thanks to the good results obtained, the Technical Review 1 in July 2022 authorized the start of Qualification for those technical bricks. From the beginning of the TVs manufacturing in January 2023 until the end of the tests in February 2024, this phase provided valuable results and it allows the definition of a qualified domain:
• FC assembly of 15x15mm² die with 900 I/O bumps
• FC assembly of 14.4x13.8mm² die with 2208 I/O bumps
• Underfill of die
• Encapsulation of FC modules
A maturity level was stated and validated at TRL6.
SIP-D demonstrator integrated by design those technological bricks. It passed ESCC test sequences in environmental conditions representative of Space applications. The maturity level was finally stated as equivalent to TRL6-7.
In parallel, an additional branch of work was developed for integrating very high density dies, such as specified in the NG-ULTRA FPGA family of NanoXplore. After a trade-off analysis of the solutions for this specific implementation and routing, a work plan has been followed:
• first trials on PCB made by ACB
• then, assemblies on SLP substrates outsourced at AT&S
After a successful phase of FC assembly evaluation of 15x15mm² dies with approx. 4400 I/O bumps, we started the design of the SIP ULTRA300 embedding a core processing function based on the NX ULTRA300 FPGA die (with approx. 6800 I/O bumps) newly manufactured by ST Microelectronics. The first samples of the SIP were delivered in March 2024 to NanoXplore
The State-of-the-Art (SoA) and the market and supply-chain analyses confirmed COMAP-4S project is compatible with the main objectives of the relevant European space road maps. Furthermore, the requirements applicable to the technologies (HDI PCB, thermal management, and SIP & assembly technologies) were specified towards the targeted objectives.
After selecting low CTE materials suitable for the intended application, PCBs were defined and manufactured. A test plan, according to ECSS PCB qualification standard, was applied to the TVs. It resulted into success and it is stated that the PCB technology used demonstrated an unmatched reliability up to 4 levels of stacked microvias with small dimensions. Outcomes of this task surpass by a multitude the current SoA HDI PCB technology used for ESA. The results were presented at IPC APEX 2023.
Based on the packaging specification, where SIP is characterized vs its thermal dissipation level, different thermal management concepts were modelled and solutions adapted to each class were identified. First thermal TVs were assembled and calibrated in 2021. After testing, an iterative process was engaged to develop and test thermal TVs more representative of real dissipating modules. The experimental results showed the capability for molding SIP by various processes, with packages able to manage power dissipation of the embedded dies up to 5W, in agreement with the simulation results. The thermal management solution was tested and characterized also in the SIP-D demonstrator at the last phase of the project. Solutions for higher dissipation levels (metal lids or structures included in the molding) could not be fully evaluated in environmental test conditions.
During the 1st phase of the project, the FC assembly technologies (materials and processes) were evaluated according to a test sequence based on applicable ESCC specifications.
Thanks to the good results obtained, the Technical Review 1 in July 2022 authorized the start of Qualification for those technical bricks. From the beginning of the TVs manufacturing in January 2023 until the end of the tests in February 2024, this phase provided valuable results and it allows the definition of a qualified domain:
• FC assembly of 15x15mm² die with 900 I/O bumps
• FC assembly of 14.4x13.8mm² die with 2208 I/O bumps
• Underfill of die
• Encapsulation of FC modules
A maturity level was stated and validated at TRL6.
SIP-D demonstrator integrated by design those technological bricks. It passed ESCC test sequences in environmental conditions representative of Space applications. The maturity level was finally stated as equivalent to TRL6-7.
In parallel, an additional branch of work was developed for integrating very high density dies, such as specified in the NG-ULTRA FPGA family of NanoXplore. After a trade-off analysis of the solutions for this specific implementation and routing, a work plan has been followed:
• first trials on PCB made by ACB
• then, assemblies on SLP substrates outsourced at AT&S
After a successful phase of FC assembly evaluation of 15x15mm² dies with approx. 4400 I/O bumps, we started the design of the SIP ULTRA300 embedding a core processing function based on the NX ULTRA300 FPGA die (with approx. 6800 I/O bumps) newly manufactured by ST Microelectronics. The first samples of the SIP were delivered in March 2024 to NanoXplore
Most of results are good and very valuable. As best examples, PCB from ACB and SLP from AT&S, with the associated assembly and packaging technologies developed and tested by Safran can already open to future uses by providing packaging solutions beyond the SoA in terms of integration. Moreover the concept of SIP-ULTRA300, packaged by Safran embedding the FPGA die and a triplication of memories in the same footprint and pinout as a standard Ultra300 package seems very solid and well advanced, and needs now to be confirmed by NX as a future solution for its customers. The SIP concept is a very big challenge in ESA roadmap. COMAP-4S beneficiaries have shown they are promising providers for these packaging and assemblies.
The turnover increase and the social indicators in participating SMEs can show also the favourable impact of COMAP-4S
The turnover increase and the social indicators in participating SMEs can show also the favourable impact of COMAP-4S