The data transmission rate has drastically increased over the last years. This trend will continue and accelerate through autonomous driving, 5G communication, and climate change. In data transfer, positioning, ecological and environmental survey, satellites are indispensable. New technological developments and business models call for more specialized and smaller satellites.
The space applications market is undergoing a substantial transformation, with new business models and an increased use of deeply integrated electronics on board satellites, for digital or analog functions. Such miniaturized equipment allows drastic reductions of the mass and finally cheaper launches per satellite.
However, despite the DSM technologies currently used for manufacturing electronic components for space, efficient and competitive packaging of large components remains a roadblock for downsizing satellites further.
Following-up innovative approaches developed in recent years, the main objective of this project is to design and qualify a macro-component demonstrator for space applications. It will offer unmatched figures of merit for the packaging of electronic components in space applications. This holds for interconnection density, die size, integration density, combined with a threefold cost reduction compared to conventional packages.
To meet this ambitious challenge, a work plan was deployed with progressive steps, in terms of complexity: die size, number of interconnections, routing density in the PCB and substrates, and power dissipation levels. Based on the complexity grades, different classes of SIP Digital, called “SIP-D”, “SIP-D extended”, “SIP-D extra” and “SIP-D Extra-addon”, were defined and used as specifications for designing and manufacturing representative Test Vehicles. After set-up of the assembly and packaging processes, incl. the design rules, and through iterations, the Test Vehicles (TVs) were submitted to test sequences according to ESCC standards. The results after evaluation and qualification of the technological bricks revealed their aptitude for building technological and functional demonstrators which integrate processing functions in a SIP:
• SIP ULTRA300 features very high density of implementation and routing in an organic and non-hermetic package, and pre-figures an innovative and “easy-to-use” solution for European designers of core processing units for Space
• SIP-D demonstrator features Flip-Chip (FC) assembly of 225mm² dies with full matrix of I/O bumps at 500µm pitch, implemented on Low CTE PCB having up to 4 levels of stacked microvias, encapsulated into an organic and non-hermetic package able to manage up to 5W power dissipation. This demonstrator passed successfully ESCC test sequences in environmental conditions representative of Space applications
COMAP-4S project demonstrates also the beginnings of a European supply chain, built around the beneficiaries within the Consortium and their 1st rank suppliers, and able to provide non-dependent solutions for SIP
