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Novel architectures for 0.18 micron devices

Obiettivo

As minimum feature sizes in VLSI processes are further reduced, and as already existing techniques are pursued close to their physical limit; at some time, they encounter impossibility of further extrapolation, and need some technological breakthroughs. This general trend is especially met in the evolution of elementary devices, N and P channel MOSFETs of CMOS technologies. The work to be carried out, includes application of process and device simulation for device optimisation, the fabrication and characterisation of test structures, and reliability studies.

This project will need the development of a few process steps. It will mainly rely on advanced process steps developed in ADEQUAT, and will make use of them as much as possible. For process and device simulation, it will rely on tools developed within other projects (eg STORM), on commercially available ones, and on process and device modelling work carried out in ADEQUAT.

The work on novel architectures to be evaluated includes:

- Channel engineering of MOS transistors by low temperature epitaxy and implantation of low diffusivity dopants. The goal is to achieve high channel current with high punchthrough voltage, and reduced short channel effects.
- Elevated source drain architecture by selective epitaxy to reduce constraints on ultra-shallow silicided junctions, and implantation of new dopants, allowing for a better control of lateral doping.
- Gate materials with work function close to mid-gap of silicon, resulting in a simpler process architecture (same gate material for N and P channel transistors), and thin gate dielectrics with silicon oxide/silicon nitride multilayers leading to reduced tunnel currents for the same equivalent silicon oxide thickness.

The final objective is to make a comparison between the various architectures at 0.18 micron feature sizes, and give recommendations for the most suitable device architecture, in accordance with future requirements of 0.18 micron CMOS products. These recommendations should be taken into account for the next phase, which should be devoted during years 1996 and 1997 to the execution of the applied research work aimed at the 0.18 micron CMOS generation.

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Coordinatore

Grenoble Silicium Submicronique
Indirizzo
Centre d'étude de grenoble avenue des martyrs
38041 Grenoble
Francia

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Partecipanti (6)