Objectif
Continuing progress of integrated microcircuits and microprocessors performance involves a reduction in the device size. Interconnections are increasingly determining the total delay, reliability, and limits improvement in device performance. Especially, it is important when feature size of integrated circuits is scaled down below 0.5 (m. To overcome the problems, it is necessary to implement two main innovations: high conductive metals and low-dielectric-constant materials. The main goals of the project are to integrate copper plated metallization with insulating systems based on materials with low dielectric constants and to develop architecture for interconnect systems for ultra-large-scale integration circuits. During the project the architecture and technology of copper based plated interconnects with resistivity less than 2.5 (Ohm.cm will be developed. Filling trenches and vias in low-k dielectric with critical dimensions below 0.25 (m and aspect ratio up to 5:1 will be investigated. Approaches to combine copper electroless and electrolytic plating for interconnection systems will be proposed. Influence of external magnetic field and pulse plating on the microstructure and performance of copper based metallization will be determined. The co-operation between European Community and New Independent States countries scientists in framework of this project will be of mutual benefit and lead to major advance in ultra-large-scale integration circuits metallization.
Appel à propositions
Data not availableRégime de financement
Data not availableCoordinateur
3001 Leuven
Belgique