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Heterogeneous Chip Multiprocessor Design

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Innovation and chips

Chip multiprocessors (CMPs) are an effective way of squeezing more processing power on to smaller spaces. Switching from homogenous to heterogeneous CMPs will help advance this process, and an EU-funded project has come up with design tools to facilitate this.

Digital Economy icon Digital Economy

Computer software and applications are becoming exponentially more complex and demanding of processing power. This raises the urgent need for novel architectures that boost both processing power and energy efficiency. One promising avenue concerns CMPs, with the International Technology Roadmap for Semiconductors (ITRS) projecting that the number of cores in a CMP will rise dramatically in the coming years. Often, manufacturers use homogeneous chips as cores in the multiprocessor, which is not an efficient use of limited space. Funded by the EU's Seventh Framework Programme (FP7), the 'Heterogeneous chip multiprocessor design' (HTCMP) project has addressed this challenge by using chips of varying capacity in multiprocessors. The project focused on a number of design issues. These included effective distribution of the available area among the processor cores and the memory blocks (cache), memory hierarchy design, the selection of processors and their types from the processor pool, and thread and data distribution. HTCMP worked on developing new techniques for compiler-based techniques for heterogeneous CMPs, which are currently lagging behind advances in circuitry and architecture. By closing this gap with effective compilation support, HTCMP will make the programming of these new architectures easier. During its second phase, HTCMP devoted its efforts to thread and data distribution, communication reduction and advanced optimisation. Towards its goal of facilitating the development of heterogeneous CMPs, the project created a heterogeneous network-on-chip (NoC) design algorithm. In addition, HTCMP also identified ways to minimise the costs and maximise the reliability of 3D NoC communications architectures.

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