High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems

Información del proyecto

ISOLDE

Identificador del acuerdo de subvención: 101112274

DOI

10.3030/101112274

Fecha de la firma de la CE 12 Mayo 2023

Fecha de inicio 1 Mayo 2023

Fecha de finalización 30 Abril 2026

Financiado con arreglo a

• Digital, Industry and Space

Coste total

€ 39 410 109,71

Aportación de la UE

€ 11 582 733,37

Coordinado por

INFINEON TECHNOLOGIES AG
Germany

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (12)

Requirements & specifications on architecture, hardware and software modules and IPs
Description of demonstrators architecture
Intermediate report on foundational IP cores

Report on WP2 work

Safety & Security modules prototype implementation

Prototypes implementation ready for Safety & Security modules, in FPGA

Accelerators prototype implementation

Initial version of the accelerator prototypes, finalized interfaces

Demonstrators Requirements & Specifications
Consolidated Demonstrators Requirements & Specifications
Intermediate Report on Dissemination Activities

Status update on the Dissemination Activities

Initial report on foundational IP cores

Describing unmodified CVA6 and first tasks

Strategic note on Open-source distribution and successful Business Models, incl. status of NewCo

Strategic note on open-source distribution and successful Business Models, incl. status of NewCo

Initial plan on dissemination & exploitation
Initial Architecture Definition

Initial architecture Definition for Safety & Security modules – internal architecture of each component, the ISA for accelerators

Data sets, microdata, etc (1)

Overview of planned IP releases via Virtual Repository and other distribution mechanisms

Publicaciones

Peer reviewed articles (3)

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

Autores: Xavier Carril, Charalampos Kardaris, Jordi Ribes-GonzáLez, Oriol Farràs, Carles Hernandez, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó
Publicado en: ACM Transactions on Reconfigurable Technology and Systems, Edición 17, 2024, ISSN 1936-7406
Editor: Association for Computing Machinery (ACM)
DOI: 10.1145/3675172

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine

Autores: Prasad, Arpan Suravi; Scherer, Moritz; Conti, Francesco; Rossi, Davide; Di Mauro, Alfio; Eggimann, Manuel; Gómez, Jorge Tómas; Li, Ziyun; Sarwar, Syed Shakib; Wang, Zhao; De Salvo, Barbara; Benini, Luca
Publicado en: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Editor: IEEE
DOI: 10.1109/JSSC.2024.3385987

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs

Autores: Pablo Andreu, Sergi Alcaide, Pedro Lopez, Jaume Abella, Carles Hernandez
Publicado en: Future Generation Computer Systems, Edición 163, 2024, ISSN 0167-739X
Editor: Elsevier BV
DOI: 10.1016/j.future.2024.107518

Conference proceedings (13)

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites

Autores: Emanuele Valpreda, Roberto Morelli, Antonio Sciarappa, Davide Di Ienno, Carlo Ciancarelli, Paolo Serri, Valeria Parascandolo, Antonio Leboffe, Dario Pascucci, Daniele Gregori, Mattia Paladino, Daniele Jahier Pagliari, Alessio Burrello, Sara Vinco, Gianv
Publicado en: 2025
Editor: RISC-V in Space workshop

The European Chips Act, The ISOLDE Project, and Open-Source Hardware

Autores: Krenn, Willibald; Wilson, Andrew; Suresh, Ambily; Freiberger, Manuel
Publicado en: 2024 Argentine Conference on Electronics (CAE), 2024
DOI: 10.5281/ZENODO.15479371

TIE Micro – Chiplets and Next-gen Packaging

Autores: Cătălin Bogdan Ciobanu, Dan Manolescu, Roxana Vlăduţă, Luciana Chiţu, Cosmin Moisă, Marcel Manofu, Paul Svasta
Publicado en: 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME), 2024
Editor: IEEE
DOI: 10.1109/SIITME63973.2024.10814902

A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation

Autores: Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich
Publicado en: MBMV 2024 Proceedings, Edición 2024, 2024, ISBN 978-3-8007-6267-5
Editor: VDE

A Hardware Accelerator for Secure Communications through Post Quantum Cryptography

Autores: Suresh, Ambily; Wilson, Andrew; Gigena-Ivanovich, Diego; Freiberger, Manuel; Krenn, Willibald
Publicado en: 2025
Editor: Zenodo and RISC-V in SPACE Conference
DOI: 10.5281/ZENODO.15480569

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure

Autores: Mehlhop, Sven; Oppenheimer, Frank; Walter, Jörg
Publicado en: 2025
DOI: 10.5281/ZENODO.16418944

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks

Autores: Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain
Publicado en: Embedded Real Time Systems (ERST) 2024 conference, Edición 2024, 2024
Editor: HAL

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project

Autores: Fornaciari William; Reghenzani Federico; Agosta Giovanni; Zoni Davide; Galimberti Andrea; Conti Francesco; Tortorella Yvan; Parisi Emanuele; Barchi Francesco; Bartolini Andrea; Acquaviva Andrea; Gregori Daniele; Cognetta Salvatore; Ciancarelli Carlo; Lebo
Publicado en: Proceedings of Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023, Edición 14385, 2023, ISBN 978-3-031-46077-7
Editor: Springer Nature Switzerland
DOI: 10.1007/978-3-031-46077-7_24

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Autores: Perotti, Matteo; Zhang, Yichao; Cavalcante, Matheus; Mustafa, Enis; Benini, Luca
Publicado en: DATE 2024 Conference Proceedings, Edición 2024, 2024
Editor: IEEE
DOI: 10.48550/arxiv.2401.04012

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

Autores: Sarraseca Julian, Marcel; Alcaide Portet, Sergi; Fuentes Díaz, Francisco Javier; Rodríguez Rivas, Juan Carlos; Chang, Feng; Lasfar, Ilham; Canal Corretger, Ramon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume
Publicado en: IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, Edición 2023, 2023, ISBN 979-8-3503-4135-5
Editor: IEEE
DOI: 10.1109/iolts59296.2023.10224867

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story

Autores: Fuentes, Francisco; Alcaide Portet, Sergi; Casanova, Raimon; Abella Ferrer, Jaume
Publicado en: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, Edición 2023, 2023, ISBN 979-8-3503-1500-4
Editor: IEEE
DOI: 10.1109/dft59622.2023.10313565

Model Predictive Control Acceleration on RISC-V

Autores: Kostal, Martin
Publicado en: 2025
DOI: 10.5281/ZENODO.15556757

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems

Autores: Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich
Publicado en: MBMV 2024 Proceedings, Edición 2024, 2024, ISBN 978-3-8007-6267-5
Editor: VDE

Other (7)

Fast RISC-V Firmware Validation with QEMU

Autores: Haxel, Frederik
Publicado en: 2024
DOI: 10.5281/ZENODO.15535717

Bridging Domains in Large-scale Complex and Critical Systems, 2025 Ed.

Autores: Robinson, Charles; Lalis, Spyros; Le Phuoc, Danh; Zoitl, Alois; Fratu, Octavian
Publicado en: 2025
DOI: 10.5281/ZENODO.14920026

On-chip Traffic Injection to Counteract Timing Side-Channel Attacks

Autores: Fuentes Diaz, Francisco Javier; Alcaide, Sergi; Casanova Mohr, Raimon; Abella, Jaume
Publicado en: 2024
DOI: 10.5281/ZENODO.15576718

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Autores: Perotti, Matteo; Riedel, Samuel; Cavalcante, Matheus; BENINI, LUCA
Publicado en: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
DOI: 10.48550/ARXIV.2309.10137

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites

Autores: Valpreda, Emanuele; Morelli, Roberto; Sciarappa, Antonio; Di Ienno, Davide; Ciancarelli, Carlo; Serri, Paolo; Parascandolo, Valeria; Leboffe, Antonio; Pascucci, Dario; Gregori, Daniele; Paladino, Mattia; JAHIER PAGLIARI, DANIELE; Burrello, Alessio; Urgese, Gianvito; Vinco, Sara; Martina, Maurizio; Masera, Guido; Fornaciari, William; Reghenzani, Federico; Galimberti, Andrea; ZONI, DAVIDE; Agosta, Giovanni; Acquaviva, Andrea; Conti, Francesco
Publicado en: 2025
DOI: 10.5281/ZENODO.15599222

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains

Autores: Abella, Jaume; Cazorla, Francisco J.; Alcaide, Sergi; Paulitsch, Michael; Peng, Yang; Gouveia, Inês Pinto
Publicado en: (White Paper), Edición 2023, 2023
Editor: ArXiv
DOI: 10.48550/arxiv.2307.11940

An Open-Source Safety Monitor Co-Processor for RISC-V Leveraging Contract-Based Design and Configurable Monitors

Autores: Mehlhop, Sven; Walter, Jörg; Oppenheimer, Frank
Publicado en: 2025
DOI: 10.13140/RG.2.2.12593.90728