High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems

Información del proyecto

ISOLDE

Identificador del acuerdo de subvención: 101112274

DOI

10.3030/101112274

Fecha de la firma de la CE 12 Mayo 2023

Fecha de inicio 1 Mayo 2023

Fecha de finalización 31 Octubre 2026

Financiado con arreglo a

• Digital, Industry and Space

Coste total

€ 38 731 434,72

Aportación de la UE

€ 11 380 593,69

Coordinado por

INFINEON TECHNOLOGIES AG
Germany

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (12)

Requirements & specifications on architecture, hardware and software modules and IPs
Description of demonstrators architecture
Intermediate report on foundational IP cores

Report on WP2 work

Safety & Security modules prototype implementation

Prototypes implementation ready for Safety & Security modules, in FPGA

Accelerators prototype implementation

Initial version of the accelerator prototypes, finalized interfaces

Demonstrators Requirements & Specifications
Consolidated Demonstrators Requirements & Specifications
Intermediate Report on Dissemination Activities

Status update on the Dissemination Activities

Initial report on foundational IP cores

Describing unmodified CVA6 and first tasks

Strategic note on Open-source distribution and successful Business Models, incl. status of NewCo

Strategic note on open-source distribution and successful Business Models, incl. status of NewCo

Initial plan on dissemination & exploitation
Initial Architecture Definition

Initial architecture Definition for Safety & Security modules – internal architecture of each component, the ISA for accelerators

Data sets, microdata, etc (1)

Overview of planned IP releases via Virtual Repository and other distribution mechanisms

Publicaciones

Conference proceedings (35)

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance

Autores: Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
Publicado en: 22nd ACM International Conference on Computing Frontiers, 2025
Editor: Association for Computing Machinery

Porting OpenEMS and Apache StreamPipes energy management software to freshly developed RISC-V system software stacks

Autores: Holger Blasum, Darshak Sheladiya, Jan Reinhard, Florian Krebs, David Engraf, Samuel Ardaya-Lieb, Frederik Haxel, Dominik Riemer, George Suciu, Mari-Anais Sachian
Publicado en: Embedded Real Time Systems (ERTS) 2026, 2026
Editor: Société de l'électricité, de l'électronique et des technologies de l'information et de la communication

The European Chips Act, The ISOLDE Project, and Open-Source Hardware

Autores: Krenn, Willibald; Wilson, Andrew; Suresh, Ambily; Freiberger, Manuel
Publicado en: 2024 Argentine Conference on Electronics (CAE), 2024
Editor: IEEE
DOI: 10.5281/ZENODO.15479371

Bridging Domains in Large-scale Complex and Critical Systems, 2025 Ed.

Autores: Robinson, Charles; Lalis, Spyros; Le Phuoc, Danh; Zoitl, Alois; Fratu, Octavian
Publicado en: 4th Whitepaper Discussions on Complex & Critical Systems (HiPEAC25), 2025
Editor: Open Phytoliths Community
DOI: 10.5281/ZENODO.14920026

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors

Autores: Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini
Publicado en: DATE 2025 Conference, 2025
Editor: IEEE

MEbots: Integrating a RISC-V Virtual Platform with a Robotic Simulator for Energy-aware Design

Autores: Giovanni Pollo, Mohamed Amine Hamdi, Matteo Risso, Lorenzo Ruotolo, Pietro Furbatto, Matteo Isoldi, Yukai Chen, Alessio Burrello, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari, Sara Vinco
Publicado en: 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2026
Editor: IEEE
DOI: 10.1109/ISLPED65674.2025.11261755

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL

Autores: Robin Sehm, Christian Ewert, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Publicado en: 2025 28th Euromicro Conference on Digital System Design (DSD), 2025
Editor: IEEE
DOI: 10.1109/DSD67783.2025.00013

Review of open neuromorphic architectures and a first integration in the RISC-V PULP platform

Autores: Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese
Publicado en: 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2024
Editor: IEEE
DOI: 10.1109/MCSOC60832.2023.00076

TIE Micro – Chiplets and Next-gen Packaging

Autores: Cătălin Bogdan Ciobanu, Dan Manolescu, Roxana Vlăduţă, Luciana Chiţu, Cosmin Moisă, Marcel Manofu, Paul Svasta
Publicado en: 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME), 2024
Editor: IEEE
DOI: 10.1109/SIITME63973.2024.10814902

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor

Autores: Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini
Publicado en: Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025
Editor: ACM
DOI: 10.1145/3719276.3725172

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites

Autores: Valpreda, Emanuele; Morelli, Roberto; Sciarappa, Antonio; Di Ienno, Davide; Ciancarelli, Carlo; Serri, Paolo; Parascandolo, Valeria; Leboffe, Antonio; Pascucci, Dario; Gregori, Daniele; Paladino, Mattia; JAHIER PAGLIARI, DANIELE; Burrello, Alessio; Urgese, Gianvito; Vinco, Sara; Martina, Maurizio; Masera, Guido; Fornaciari, William; Reghenzani, Federico; Galimberti, Andrea; ZONI, DAVIDE; Agosta, Giovanni; Acquaviva, Andrea; Conti, Francesco
Publicado en: RISC-V in Space Workshop 2025, 2025
Editor: RISC-V in Space workshop
DOI: 10.5281/ZENODO.15599223

A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation

Autores: Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich
Publicado en: MBMV 2024 Proceedings, Edición 2024, 2024, ISBN 978-3-8007-6267-5
Editor: VDE

A Hardware Accelerator for Secure Communications through Post Quantum Cryptography

Autores: Suresh, Ambily; Wilson, Andrew; Gigena-Ivanovich, Diego; Freiberger, Manuel; Krenn, Willibald
Publicado en: RISC-V in SPACE Conference 2025, 2025
Editor: Zenodo and RISC-V in SPACE Conference
DOI: 10.5281/ZENODO.15480570

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure

Autores: Mehlhop, Sven; Oppenheimer, Frank; Walter, Jörg
Publicado en: Forum on specification & Design Languages, 2025
Editor: OpenAIRE
DOI: 10.5281/ZENODO.16418943

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks

Autores: Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain
Publicado en: Embedded Real Time Systems (ERST) 2024 conference, Edición 2024, 2024
Editor: HAL

Application of Tiny RISC-V

Autores: Jaume Abella, Sergi Alcaide, Eric Rufart, Leonidas Kosmidis, Alexandru Puscasu, Razvan Stancu, Octavian Buiu, Catalin Bogdan Ciobanu, Costin-Emanuel Vasile, Calin Bira
Publicado en: Proceedings of the 23rd ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2026
Editor: Association for Computing Machinery
DOI: 10.1145/3801488.3807978

Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs

Autores: Federico Nicolas Peccia, Frederik Haxel, Oliver Bringmann
Publicado en: IEEE International Conference on Computer-Aided Design, 2025
Editor: IEEE

Explorative surveying RISC-V open hardware and specifications for mixed-critical systems

Autores: Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya, George Violettas
Publicado en: RISC-V Summit Europe 2024
Editor: RISC-V

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project

Autores: Fornaciari William; Reghenzani Federico; Agosta Giovanni; Zoni Davide; Galimberti Andrea; Conti Francesco; Tortorella Yvan; Parisi Emanuele; Barchi Francesco; Bartolini Andrea; Acquaviva Andrea; Gregori Daniele; Cognetta Salvatore; Ciancarelli Carlo; Lebo
Publicado en: Proceedings of Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023, Edición 14385, 2023, ISBN 978-3-031-46077-7
Editor: Springer Nature Switzerland
DOI: 10.1007/978-3-031-46077-7_24

On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation

Autores: Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella
Publicado en: Embedded Real Time Systems (ERTS) 2026, 2026
Editor: Société de l'électricité, de l'électronique et des technologies de l'information et de la communication

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution

Autores: Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini
Publicado en: Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025
Editor: Association for Computing Machinery (ACM)
DOI: 10.1145/3719276.3725186

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Autores: Perotti, Matteo; Zhang, Yichao; Cavalcante, Matheus; Mustafa, Enis; Benini, Luca
Publicado en: DATE 2024 Conference Proceedings, Edición 2024, 2024
Editor: IEEE
DOI: 10.48550/arxiv.2401.04012

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

Autores: Sarraseca Julian, Marcel; Alcaide Portet, Sergi; Fuentes Díaz, Francisco Javier; Rodríguez Rivas, Juan Carlos; Chang, Feng; Lasfar, Ilham; Canal Corretger, Ramon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume
Publicado en: IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, Edición 2023, 2023, ISBN 979-8-3503-4135-5
Editor: IEEE
DOI: 10.1109/iolts59296.2023.10224867

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads

Autores: Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus Cavalcante, Davide Rossi, Luca Benini
Publicado en: IEEE 35th International Conference on Application Specific Systems (ASAP) 2024, 2024
Editor: IEEE

An Open-Source Safety Monitor Co-Processor for RISC-V Leveraging Contract-Based Design and Configurable Monitors

Autores: Mehlhop, Sven; Walter, Jörg; Oppenheimer, Frank
Publicado en: Forum on specification & Design Languages, 2025
Editor: OFFIS
DOI: 10.13140/RG.2.2.12593.90728

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story

Autores: Fuentes, Francisco; Alcaide Portet, Sergi; Casanova, Raimon; Abella Ferrer, Jaume
Publicado en: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, Edición 2023, 2023, ISBN 979-8-3503-1500-4
Editor: IEEE
DOI: 10.1109/dft59622.2023.10313565

Adversarial Attacks Detection for Self-Driving Cars using GPUs

Autores: Ștefan Cristian Jarcău, Ionuț Alexandru Oprea, Alexandru Mihai Andrei, Robert Ionuț Duca,Bogdan Valentin Floricescu, Cătălin Bogdan Ciobanu, Lucian Mircea Sasu, Sorin Mihai Grigorescu,
Publicado en: in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025), 2025
Editor: IEEE

TRISTAN & ISOLDE Chips-JU RISC-V Projects

Autores: Cătălin Bogdan Ciobanu, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Dominik Baumann, Alexandru Pușcașu, Mihai Gologanu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, J
Publicado en: in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2025 conference, 2025
Editor: Springer

Model Predictive Control Acceleration on RISC-V

Autores: Kostal, Martin
Publicado en: HIPEAC 2025, 2025
Editor: Open AIRE
DOI: 10.5281/ZENODO.15556756

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices

Autores: Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari
Publicado en: Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2025
Editor: ACM
DOI: 10.1145/3637543.3652873

Minutiae Extraction Optimization for ARM and RISC-V

Autores: Andreea Violeta Pascociu, Andrei Eduard Solomon, Csaba Zoltán Kertész, Cătălin Bogdan Ciobanu
Publicado en: in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025), 2025
Editor: IEEE

Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching

Autores: Matthias Rupp, Stefan Wallentowitz
Publicado en: Lecture Notes in Computer Science, Edición 14842, 2024
Editor: Springer

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA

Autores: Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese
Publicado en: Communications in Computer and Information Science, Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2026
Editor: Springer Nature Switzerland
DOI: 10.1007/978-3-032-25311-8_10

Scalable 16-N point FFT Accelerator

Autores: Răzvan Stancu, Mihai Gologanu, Alexandru Pușcasu, Cătălin Bogdan Ciobanu,Octavian Buiu
Publicado en: in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025), 2025
Editor: IEEE

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems

Autores: Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich
Publicado en: MBMV 2024 Proceedings, Edición 2024, 2024, ISBN 978-3-8007-6267-5
Editor: VDE

Peer reviewed articles (8)

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

Autores: Xavier Carril, Charalampos Kardaris, Jordi Ribes-GonzáLez, Oriol Farràs, Carles Hernandez, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó
Publicado en: ACM Transactions on Reconfigurable Technology and Systems, Edición 17, 2024, ISSN 1936-7406
Editor: Association for Computing Machinery (ACM)
DOI: 10.1145/3675172

Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform

Autores: Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
Publicado en: IEEE Transactions on Circuits and Systems for Artificial Intelligence, Edición 1, 2024, ISSN 2996-6647
Editor: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCASAI.2024.3459412

Benchmarking WebAssembly for Embedded Systems

Autores: Konrad Moron, Stefan Wallentowitz
Publicado en: ACM Transactions on Architecture and Compiler Optimizations, Edición 22, 3, 2025, ISSN 1544-3973
Editor: Association for Computing Machinery
DOI: 10.1145/3736169

Compatibility Ratio as a Guideline for Hardware/DNN Co-Design of Embedded Accelerators

Autores: Lukas Groth, Andrija Neskovic, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Publicado en: ACM Transactions on Embedded Computing Systems, 2026, ISSN 1539-9087
Editor: Association for Computing Machinery (ACM)
DOI: 10.1145/3841637

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine

Autores: Prasad, Arpan Suravi; Scherer, Moritz; Conti, Francesco; Rossi, Davide; Di Mauro, Alfio; Eggimann, Manuel; Gómez, Jorge Tómas; Li, Ziyun; Sarwar, Syed Shakib; Wang, Zhao; De Salvo, Barbara; Benini, Luca
Publicado en: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Editor: IEEE
DOI: 10.1109/JSSC.2024.3385987

MATCH: Model-Aware TVM-Based Compilation for Heterogeneous Edge Devices

Autores: Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda, Josse Van Delm, Arne Symons, Luca Benini, Marian Verhelst, Daniele Jahier Pagliari, Alessio Burrello
Publicado en: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Edición 44, 2025, ISSN 0278-0070
Editor: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCAD.2025.3556967

Joint Pruning and Channel-Wise Mixed-Precision Quantization for Efficient Deep Neural Networks

Autores: Beatrice Alessandra Motetti, Matteo Risso, Alessio Burrello, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Publicado en: IEEE Transactions on Computers, Edición 73, 2024, ISSN 0018-9340
Editor: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TC.2024.3449084

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs

Autores: Pablo Andreu, Sergi Alcaide, Pedro Lopez, Jaume Abella, Carles Hernandez
Publicado en: Future Generation Computer Systems, Edición 163, 2024, ISSN 0167-739X
Editor: Elsevier BV
DOI: 10.1016/j.future.2024.107518

Other (4)

Fast RISC-V Firmware Validation with QEMU

Autores: Haxel, Frederik
Publicado en: 2024
Editor: Open AIRE
DOI: 10.5281/ZENODO.15535717

On-chip Traffic Injection to Counteract Timing Side-Channel Attacks

Autores: Fuentes Diaz, Francisco Javier; Alcaide, Sergi; Casanova Mohr, Raimon; Abella, Jaume
Publicado en: (Whitepaper), 2024
Editor: Open AIRE
DOI: 10.5281/ZENODO.15576718

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Autores: Perotti, Matteo; Riedel, Samuel; Cavalcante, Matheus; BENINI, LUCA
Publicado en: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
Editor: IEEE
DOI: 10.48550/ARXIV.2309.10137

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains

Autores: Abella, Jaume; Cazorla, Francisco J.; Alcaide, Sergi; Paulitsch, Michael; Peng, Yang; Gouveia, Inês Pinto
Publicado en: (Whitepaper), 2023
Editor: ArXiv
DOI: 10.48550/ARXIV.2307.11940

Book chapters (1)

Characterising Physical Memory Access Pattern Impact on RISC-V Softcore Performance: A Microbenchmark Study

Autores: Hsin-Kun Lin, Wadid Foudhaili, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Publicado en: Lecture Notes in Computer Science, Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2026
Editor: Springer Nature Switzerland
DOI: 10.1007/978-3-032-29365-7_6

Thesis and dissertations (3)

Extinderea compilatorului LLVM pentru arhitectura RISC-V

Autores: Vlad-Mihai Popescu
Publicado en: 2025
Editor: Transilvania University of Brasov

Extensie a setului de instrucțiuni RISC-V

Autores: Alexandru Pușcașu
Publicado en: 2025
Editor: Transilvania University of Brasov

Accelerarea Hardware a conversiei spațiilor de culoare YUV-RGB pe procesoarele RISC-V

Autores: Mariana-Luciana Mitu
Publicado en: 2025
Editor: Transilvania University of Brasov