High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems

Informations projet

ISOLDE

N° de convention de subvention: 101112274

DOI

10.3030/101112274

Date de signature de la CE 12 Mai 2023

Date de début 1 Mai 2023

Date de fin 31 Octobre 2026

Financé au titre de

• Digital, Industry and Space

Coût total

€ 38 731 434,72

Contribution de l’UE

€ 11 380 593,69

Coordonné par

INFINEON TECHNOLOGIES AG
Germany

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Documents, reports (12)

Requirements & specifications on architecture, hardware and software modules and IPs
Description of demonstrators architecture
Intermediate report on foundational IP cores

Report on WP2 work

Safety & Security modules prototype implementation

Prototypes implementation ready for Safety & Security modules, in FPGA

Accelerators prototype implementation

Initial version of the accelerator prototypes, finalized interfaces

Demonstrators Requirements & Specifications
Consolidated Demonstrators Requirements & Specifications
Intermediate Report on Dissemination Activities

Status update on the Dissemination Activities

Initial report on foundational IP cores

Describing unmodified CVA6 and first tasks

Strategic note on Open-source distribution and successful Business Models, incl. status of NewCo

Strategic note on open-source distribution and successful Business Models, incl. status of NewCo

Initial plan on dissemination & exploitation
Initial Architecture Definition

Initial architecture Definition for Safety & Security modules – internal architecture of each component, the ISA for accelerators

Data sets, microdata, etc (1)

Overview of planned IP releases via Virtual Repository and other distribution mechanisms

Publications

Conference proceedings (35)

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance

Auteurs: Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
Publié dans: 22nd ACM International Conference on Computing Frontiers, 2025
Éditeur: Association for Computing Machinery

Porting OpenEMS and Apache StreamPipes energy management software to freshly developed RISC-V system software stacks

Auteurs: Holger Blasum, Darshak Sheladiya, Jan Reinhard, Florian Krebs, David Engraf, Samuel Ardaya-Lieb, Frederik Haxel, Dominik Riemer, George Suciu, Mari-Anais Sachian
Publié dans: Embedded Real Time Systems (ERTS) 2026, 2026
Éditeur: Société de l'électricité, de l'électronique et des technologies de l'information et de la communication

The European Chips Act, The ISOLDE Project, and Open-Source Hardware

Auteurs: Krenn, Willibald; Wilson, Andrew; Suresh, Ambily; Freiberger, Manuel
Publié dans: 2024 Argentine Conference on Electronics (CAE), 2024
Éditeur: IEEE
DOI: 10.5281/ZENODO.15479371

Bridging Domains in Large-scale Complex and Critical Systems, 2025 Ed.

Auteurs: Robinson, Charles; Lalis, Spyros; Le Phuoc, Danh; Zoitl, Alois; Fratu, Octavian
Publié dans: 4th Whitepaper Discussions on Complex & Critical Systems (HiPEAC25), 2025
Éditeur: Open Phytoliths Community
DOI: 10.5281/ZENODO.14920026

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors

Auteurs: Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini
Publié dans: DATE 2025 Conference, 2025
Éditeur: IEEE

MEbots: Integrating a RISC-V Virtual Platform with a Robotic Simulator for Energy-aware Design

Auteurs: Giovanni Pollo, Mohamed Amine Hamdi, Matteo Risso, Lorenzo Ruotolo, Pietro Furbatto, Matteo Isoldi, Yukai Chen, Alessio Burrello, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari, Sara Vinco
Publié dans: 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2026
Éditeur: IEEE
DOI: 10.1109/ISLPED65674.2025.11261755

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL

Auteurs: Robin Sehm, Christian Ewert, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Publié dans: 2025 28th Euromicro Conference on Digital System Design (DSD), 2025
Éditeur: IEEE
DOI: 10.1109/DSD67783.2025.00013

Review of open neuromorphic architectures and a first integration in the RISC-V PULP platform

Auteurs: Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese
Publié dans: 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2024
Éditeur: IEEE
DOI: 10.1109/MCSOC60832.2023.00076

TIE Micro – Chiplets and Next-gen Packaging

Auteurs: Cătălin Bogdan Ciobanu, Dan Manolescu, Roxana Vlăduţă, Luciana Chiţu, Cosmin Moisă, Marcel Manofu, Paul Svasta
Publié dans: 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME), 2024
Éditeur: IEEE
DOI: 10.1109/SIITME63973.2024.10814902

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor

Auteurs: Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini
Publié dans: Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025
Éditeur: ACM
DOI: 10.1145/3719276.3725172

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites

Auteurs: Valpreda, Emanuele; Morelli, Roberto; Sciarappa, Antonio; Di Ienno, Davide; Ciancarelli, Carlo; Serri, Paolo; Parascandolo, Valeria; Leboffe, Antonio; Pascucci, Dario; Gregori, Daniele; Paladino, Mattia; JAHIER PAGLIARI, DANIELE; Burrello, Alessio; Urgese, Gianvito; Vinco, Sara; Martina, Maurizio; Masera, Guido; Fornaciari, William; Reghenzani, Federico; Galimberti, Andrea; ZONI, DAVIDE; Agosta, Giovanni; Acquaviva, Andrea; Conti, Francesco
Publié dans: RISC-V in Space Workshop 2025, 2025
Éditeur: RISC-V in Space workshop
DOI: 10.5281/ZENODO.15599223

A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation

Auteurs: Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich
Publié dans: MBMV 2024 Proceedings, Numéro 2024, 2024, ISBN 978-3-8007-6267-5
Éditeur: VDE

A Hardware Accelerator for Secure Communications through Post Quantum Cryptography

Auteurs: Suresh, Ambily; Wilson, Andrew; Gigena-Ivanovich, Diego; Freiberger, Manuel; Krenn, Willibald
Publié dans: RISC-V in SPACE Conference 2025, 2025
Éditeur: Zenodo and RISC-V in SPACE Conference
DOI: 10.5281/ZENODO.15480570

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure

Auteurs: Mehlhop, Sven; Oppenheimer, Frank; Walter, Jörg
Publié dans: Forum on specification & Design Languages, 2025
Éditeur: OpenAIRE
DOI: 10.5281/ZENODO.16418943

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks

Auteurs: Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain
Publié dans: Embedded Real Time Systems (ERST) 2024 conference, Numéro 2024, 2024
Éditeur: HAL

Application of Tiny RISC-V

Auteurs: Jaume Abella, Sergi Alcaide, Eric Rufart, Leonidas Kosmidis, Alexandru Puscasu, Razvan Stancu, Octavian Buiu, Catalin Bogdan Ciobanu, Costin-Emanuel Vasile, Calin Bira
Publié dans: Proceedings of the 23rd ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2026
Éditeur: Association for Computing Machinery
DOI: 10.1145/3801488.3807978

Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs

Auteurs: Federico Nicolas Peccia, Frederik Haxel, Oliver Bringmann
Publié dans: IEEE International Conference on Computer-Aided Design, 2025
Éditeur: IEEE

Explorative surveying RISC-V open hardware and specifications for mixed-critical systems

Auteurs: Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya, George Violettas
Publié dans: RISC-V Summit Europe 2024
Éditeur: RISC-V

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project

Auteurs: Fornaciari William; Reghenzani Federico; Agosta Giovanni; Zoni Davide; Galimberti Andrea; Conti Francesco; Tortorella Yvan; Parisi Emanuele; Barchi Francesco; Bartolini Andrea; Acquaviva Andrea; Gregori Daniele; Cognetta Salvatore; Ciancarelli Carlo; Lebo
Publié dans: Proceedings of Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023, Numéro 14385, 2023, ISBN 978-3-031-46077-7
Éditeur: Springer Nature Switzerland
DOI: 10.1007/978-3-031-46077-7_24

On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation

Auteurs: Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella
Publié dans: Embedded Real Time Systems (ERTS) 2026, 2026
Éditeur: Société de l'électricité, de l'électronique et des technologies de l'information et de la communication

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution

Auteurs: Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, César Fuguet, Davide Rossi, Luca Benini
Publié dans: Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025
Éditeur: Association for Computing Machinery (ACM)
DOI: 10.1145/3719276.3725186

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Auteurs: Perotti, Matteo; Zhang, Yichao; Cavalcante, Matheus; Mustafa, Enis; Benini, Luca
Publié dans: DATE 2024 Conference Proceedings, Numéro 2024, 2024
Éditeur: IEEE
DOI: 10.48550/arxiv.2401.04012

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

Auteurs: Sarraseca Julian, Marcel; Alcaide Portet, Sergi; Fuentes Díaz, Francisco Javier; Rodríguez Rivas, Juan Carlos; Chang, Feng; Lasfar, Ilham; Canal Corretger, Ramon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume
Publié dans: IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, Numéro 2023, 2023, ISBN 979-8-3503-4135-5
Éditeur: IEEE
DOI: 10.1109/iolts59296.2023.10224867

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads

Auteurs: Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus Cavalcante, Davide Rossi, Luca Benini
Publié dans: IEEE 35th International Conference on Application Specific Systems (ASAP) 2024, 2024
Éditeur: IEEE

An Open-Source Safety Monitor Co-Processor for RISC-V Leveraging Contract-Based Design and Configurable Monitors

Auteurs: Mehlhop, Sven; Walter, Jörg; Oppenheimer, Frank
Publié dans: Forum on specification & Design Languages, 2025
Éditeur: OFFIS
DOI: 10.13140/RG.2.2.12593.90728

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story

Auteurs: Fuentes, Francisco; Alcaide Portet, Sergi; Casanova, Raimon; Abella Ferrer, Jaume
Publié dans: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, Numéro 2023, 2023, ISBN 979-8-3503-1500-4
Éditeur: IEEE
DOI: 10.1109/dft59622.2023.10313565

Adversarial Attacks Detection for Self-Driving Cars using GPUs

Auteurs: Ștefan Cristian Jarcău, Ionuț Alexandru Oprea, Alexandru Mihai Andrei, Robert Ionuț Duca,Bogdan Valentin Floricescu, Cătălin Bogdan Ciobanu, Lucian Mircea Sasu, Sorin Mihai Grigorescu,
Publié dans: in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025), 2025
Éditeur: IEEE

TRISTAN & ISOLDE Chips-JU RISC-V Projects

Auteurs: Cătălin Bogdan Ciobanu, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Dominik Baumann, Alexandru Pușcașu, Mihai Gologanu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, J
Publié dans: in Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2025 conference, 2025
Éditeur: Springer

Model Predictive Control Acceleration on RISC-V

Auteurs: Kostal, Martin
Publié dans: HIPEAC 2025, 2025
Éditeur: Open AIRE
DOI: 10.5281/ZENODO.15556756

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices

Auteurs: Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari
Publié dans: Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2025
Éditeur: ACM
DOI: 10.1145/3637543.3652873

Minutiae Extraction Optimization for ARM and RISC-V

Auteurs: Andreea Violeta Pascociu, Andrei Eduard Solomon, Csaba Zoltán Kertész, Cătălin Bogdan Ciobanu
Publié dans: in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025), 2025
Éditeur: IEEE

Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching

Auteurs: Matthias Rupp, Stefan Wallentowitz
Publié dans: Lecture Notes in Computer Science, Numéro 14842, 2024
Éditeur: Springer

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA

Auteurs: Michelangelo Barocci, Vittorio Fra, Enrico Macii, Gianvito Urgese
Publié dans: Communications in Computer and Information Science, Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2026
Éditeur: Springer Nature Switzerland
DOI: 10.1007/978-3-032-25311-8_10

Scalable 16-N point FFT Accelerator

Auteurs: Răzvan Stancu, Mihai Gologanu, Alexandru Pușcasu, Cătălin Bogdan Ciobanu,Octavian Buiu
Publié dans: in Proceedings of 2025 IEEE 31st International Symposium for Design and Technology in Electronic Packaging (SIITME 2025), 2025
Éditeur: IEEE

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems

Auteurs: Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich
Publié dans: MBMV 2024 Proceedings, Numéro 2024, 2024, ISBN 978-3-8007-6267-5
Éditeur: VDE

Peer reviewed articles (8)

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

Auteurs: Xavier Carril, Charalampos Kardaris, Jordi Ribes-GonzáLez, Oriol Farràs, Carles Hernandez, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó
Publié dans: ACM Transactions on Reconfigurable Technology and Systems, Numéro 17, 2024, ISSN 1936-7406
Éditeur: Association for Computing Machinery (ACM)
DOI: 10.1145/3675172

Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform

Auteurs: Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
Publié dans: IEEE Transactions on Circuits and Systems for Artificial Intelligence, Numéro 1, 2024, ISSN 2996-6647
Éditeur: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCASAI.2024.3459412

Benchmarking WebAssembly for Embedded Systems

Auteurs: Konrad Moron, Stefan Wallentowitz
Publié dans: ACM Transactions on Architecture and Compiler Optimizations, Numéro 22, 3, 2025, ISSN 1544-3973
Éditeur: Association for Computing Machinery
DOI: 10.1145/3736169

Compatibility Ratio as a Guideline for Hardware/DNN Co-Design of Embedded Accelerators

Auteurs: Lukas Groth, Andrija Neskovic, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Publié dans: ACM Transactions on Embedded Computing Systems, 2026, ISSN 1539-9087
Éditeur: Association for Computing Machinery (ACM)
DOI: 10.1145/3841637

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine

Auteurs: Prasad, Arpan Suravi; Scherer, Moritz; Conti, Francesco; Rossi, Davide; Di Mauro, Alfio; Eggimann, Manuel; Gómez, Jorge Tómas; Li, Ziyun; Sarwar, Syed Shakib; Wang, Zhao; De Salvo, Barbara; Benini, Luca
Publié dans: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Éditeur: IEEE
DOI: 10.1109/JSSC.2024.3385987

MATCH: Model-Aware TVM-Based Compilation for Heterogeneous Edge Devices

Auteurs: Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda, Josse Van Delm, Arne Symons, Luca Benini, Marian Verhelst, Daniele Jahier Pagliari, Alessio Burrello
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numéro 44, 2025, ISSN 0278-0070
Éditeur: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCAD.2025.3556967

Joint Pruning and Channel-Wise Mixed-Precision Quantization for Efficient Deep Neural Networks

Auteurs: Beatrice Alessandra Motetti, Matteo Risso, Alessio Burrello, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Publié dans: IEEE Transactions on Computers, Numéro 73, 2024, ISSN 0018-9340
Éditeur: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TC.2024.3449084

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs

Auteurs: Pablo Andreu, Sergi Alcaide, Pedro Lopez, Jaume Abella, Carles Hernandez
Publié dans: Future Generation Computer Systems, Numéro 163, 2024, ISSN 0167-739X
Éditeur: Elsevier BV
DOI: 10.1016/j.future.2024.107518

Other (4)

Fast RISC-V Firmware Validation with QEMU

Auteurs: Haxel, Frederik
Publié dans: 2024
Éditeur: Open AIRE
DOI: 10.5281/ZENODO.15535717

On-chip Traffic Injection to Counteract Timing Side-Channel Attacks

Auteurs: Fuentes Diaz, Francisco Javier; Alcaide, Sergi; Casanova Mohr, Raimon; Abella, Jaume
Publié dans: (Whitepaper), 2024
Éditeur: Open AIRE
DOI: 10.5281/ZENODO.15576718

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Auteurs: Perotti, Matteo; Riedel, Samuel; Cavalcante, Matheus; BENINI, LUCA
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
Éditeur: IEEE
DOI: 10.48550/ARXIV.2309.10137

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains

Auteurs: Abella, Jaume; Cazorla, Francisco J.; Alcaide, Sergi; Paulitsch, Michael; Peng, Yang; Gouveia, Inês Pinto
Publié dans: (Whitepaper), 2023
Éditeur: ArXiv
DOI: 10.48550/ARXIV.2307.11940

Book chapters (1)

Characterising Physical Memory Access Pattern Impact on RISC-V Softcore Performance: A Microbenchmark Study

Auteurs: Hsin-Kun Lin, Wadid Foudhaili, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Publié dans: Lecture Notes in Computer Science, Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2026
Éditeur: Springer Nature Switzerland
DOI: 10.1007/978-3-032-29365-7_6

Thesis and dissertations (3)

Extinderea compilatorului LLVM pentru arhitectura RISC-V

Auteurs: Vlad-Mihai Popescu
Publié dans: 2025
Éditeur: Transilvania University of Brasov

Extensie a setului de instrucțiuni RISC-V

Auteurs: Alexandru Pușcașu
Publié dans: 2025
Éditeur: Transilvania University of Brasov

Accelerarea Hardware a conversiei spațiilor de culoare YUV-RGB pe procesoarele RISC-V

Auteurs: Mariana-Luciana Mitu
Publié dans: 2025
Éditeur: Transilvania University of Brasov