High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems

Informazioni relative al progetto

ISOLDE

ID dell’accordo di sovvenzione: 101112274

DOI

10.3030/101112274

Data della firma CE 12 Maggio 2023

Data di avvio 1 Maggio 2023

Data di completamento 30 Aprile 2026

Finanziato da

• Digital, Industry and Space

Costo totale

€ 39 410 109,71

Contributo UE

€ 11 582 733,37

Coordinato da

INFINEON TECHNOLOGIES AG
Germany

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Documents, reports (12)

Requirements & specifications on architecture, hardware and software modules and IPs
Description of demonstrators architecture
Intermediate report on foundational IP cores

Report on WP2 work

Safety & Security modules prototype implementation

Prototypes implementation ready for Safety & Security modules, in FPGA

Accelerators prototype implementation

Initial version of the accelerator prototypes, finalized interfaces

Demonstrators Requirements & Specifications
Consolidated Demonstrators Requirements & Specifications
Intermediate Report on Dissemination Activities

Status update on the Dissemination Activities

Initial report on foundational IP cores

Describing unmodified CVA6 and first tasks

Strategic note on Open-source distribution and successful Business Models, incl. status of NewCo

Strategic note on open-source distribution and successful Business Models, incl. status of NewCo

Initial plan on dissemination & exploitation
Initial Architecture Definition

Initial architecture Definition for Safety & Security modules – internal architecture of each component, the ISA for accelerators

Data sets, microdata, etc (1)

Overview of planned IP releases via Virtual Repository and other distribution mechanisms

Pubblicazioni

Peer reviewed articles (3)

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium

Autori: Xavier Carril, Charalampos Kardaris, Jordi Ribes-GonzáLez, Oriol Farràs, Carles Hernandez, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó
Pubblicato in: ACM Transactions on Reconfigurable Technology and Systems, Numero 17, 2024, ISSN 1936-7406
Editore: Association for Computing Machinery (ACM)
DOI: 10.1145/3675172

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine

Autori: Prasad, Arpan Suravi; Scherer, Moritz; Conti, Francesco; Rossi, Davide; Di Mauro, Alfio; Eggimann, Manuel; Gómez, Jorge Tómas; Li, Ziyun; Sarwar, Syed Shakib; Wang, Zhao; De Salvo, Barbara; Benini, Luca
Pubblicato in: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Editore: IEEE
DOI: 10.1109/JSSC.2024.3385987

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs

Autori: Pablo Andreu, Sergi Alcaide, Pedro Lopez, Jaume Abella, Carles Hernandez
Pubblicato in: Future Generation Computer Systems, Numero 163, 2024, ISSN 0167-739X
Editore: Elsevier BV
DOI: 10.1016/j.future.2024.107518

Conference proceedings (13)

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites

Autori: Emanuele Valpreda, Roberto Morelli, Antonio Sciarappa, Davide Di Ienno, Carlo Ciancarelli, Paolo Serri, Valeria Parascandolo, Antonio Leboffe, Dario Pascucci, Daniele Gregori, Mattia Paladino, Daniele Jahier Pagliari, Alessio Burrello, Sara Vinco, Gianv
Pubblicato in: 2025
Editore: RISC-V in Space workshop

The European Chips Act, The ISOLDE Project, and Open-Source Hardware

Autori: Krenn, Willibald; Wilson, Andrew; Suresh, Ambily; Freiberger, Manuel
Pubblicato in: 2024 Argentine Conference on Electronics (CAE), 2024
DOI: 10.5281/ZENODO.15479371

TIE Micro – Chiplets and Next-gen Packaging

Autori: Cătălin Bogdan Ciobanu, Dan Manolescu, Roxana Vlăduţă, Luciana Chiţu, Cosmin Moisă, Marcel Manofu, Paul Svasta
Pubblicato in: 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME), 2024
Editore: IEEE
DOI: 10.1109/SIITME63973.2024.10814902

A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation

Autori: Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich
Pubblicato in: MBMV 2024 Proceedings, Numero 2024, 2024, ISBN 978-3-8007-6267-5
Editore: VDE

A Hardware Accelerator for Secure Communications through Post Quantum Cryptography

Autori: Suresh, Ambily; Wilson, Andrew; Gigena-Ivanovich, Diego; Freiberger, Manuel; Krenn, Willibald
Pubblicato in: 2025
Editore: Zenodo and RISC-V in SPACE Conference
DOI: 10.5281/ZENODO.15480569

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure

Autori: Mehlhop, Sven; Oppenheimer, Frank; Walter, Jörg
Pubblicato in: 2025
DOI: 10.5281/ZENODO.16418944

Onchip Traffic Injection to Counteract Timing Side-Channel Attacks

Autori: Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain
Pubblicato in: Embedded Real Time Systems (ERST) 2024 conference, Numero 2024, 2024
Editore: HAL

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project

Autori: Fornaciari William; Reghenzani Federico; Agosta Giovanni; Zoni Davide; Galimberti Andrea; Conti Francesco; Tortorella Yvan; Parisi Emanuele; Barchi Francesco; Bartolini Andrea; Acquaviva Andrea; Gregori Daniele; Cognetta Salvatore; Ciancarelli Carlo; Lebo
Pubblicato in: Proceedings of Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023, Numero 14385, 2023, ISBN 978-3-031-46077-7
Editore: Springer Nature Switzerland
DOI: 10.1007/978-3-031-46077-7_24

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Autori: Perotti, Matteo; Zhang, Yichao; Cavalcante, Matheus; Mustafa, Enis; Benini, Luca
Pubblicato in: DATE 2024 Conference Proceedings, Numero 2024, 2024
Editore: IEEE
DOI: 10.48550/arxiv.2401.04012

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

Autori: Sarraseca Julian, Marcel; Alcaide Portet, Sergi; Fuentes Díaz, Francisco Javier; Rodríguez Rivas, Juan Carlos; Chang, Feng; Lasfar, Ilham; Canal Corretger, Ramon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume
Pubblicato in: IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, Numero 2023, 2023, ISBN 979-8-3503-4135-5
Editore: IEEE
DOI: 10.1109/iolts59296.2023.10224867

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story

Autori: Fuentes, Francisco; Alcaide Portet, Sergi; Casanova, Raimon; Abella Ferrer, Jaume
Pubblicato in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, Numero 2023, 2023, ISBN 979-8-3503-1500-4
Editore: IEEE
DOI: 10.1109/dft59622.2023.10313565

Model Predictive Control Acceleration on RISC-V

Autori: Kostal, Martin
Pubblicato in: 2025
DOI: 10.5281/ZENODO.15556757

A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems

Autori: Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich
Pubblicato in: MBMV 2024 Proceedings, Numero 2024, 2024, ISBN 978-3-8007-6267-5
Editore: VDE

Other (7)

Fast RISC-V Firmware Validation with QEMU

Autori: Haxel, Frederik
Pubblicato in: 2024
DOI: 10.5281/ZENODO.15535717

Bridging Domains in Large-scale Complex and Critical Systems, 2025 Ed.

Autori: Robinson, Charles; Lalis, Spyros; Le Phuoc, Danh; Zoitl, Alois; Fratu, Octavian
Pubblicato in: 2025
DOI: 10.5281/ZENODO.14920026

On-chip Traffic Injection to Counteract Timing Side-Channel Attacks

Autori: Fuentes Diaz, Francisco Javier; Alcaide, Sergi; Casanova Mohr, Raimon; Abella, Jaume
Pubblicato in: 2024
DOI: 10.5281/ZENODO.15576718

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Autori: Perotti, Matteo; Riedel, Samuel; Cavalcante, Matheus; BENINI, LUCA
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
DOI: 10.48550/ARXIV.2309.10137

The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites

Autori: Valpreda, Emanuele; Morelli, Roberto; Sciarappa, Antonio; Di Ienno, Davide; Ciancarelli, Carlo; Serri, Paolo; Parascandolo, Valeria; Leboffe, Antonio; Pascucci, Dario; Gregori, Daniele; Paladino, Mattia; JAHIER PAGLIARI, DANIELE; Burrello, Alessio; Urgese, Gianvito; Vinco, Sara; Martina, Maurizio; Masera, Guido; Fornaciari, William; Reghenzani, Federico; Galimberti, Andrea; ZONI, DAVIDE; Agosta, Giovanni; Acquaviva, Andrea; Conti, Francesco
Pubblicato in: 2025
DOI: 10.5281/ZENODO.15599222

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains

Autori: Abella, Jaume; Cazorla, Francisco J.; Alcaide, Sergi; Paulitsch, Michael; Peng, Yang; Gouveia, Inês Pinto
Pubblicato in: (White Paper), Numero 2023, 2023
Editore: ArXiv
DOI: 10.48550/arxiv.2307.11940

An Open-Source Safety Monitor Co-Processor for RISC-V Leveraging Contract-Based Design and Configurable Monitors

Autori: Mehlhop, Sven; Walter, Jörg; Oppenheimer, Frank
Pubblicato in: 2025
DOI: 10.13140/RG.2.2.12593.90728