Twinning for Excellence in Reliable Electronics

Información del proyecto

TWIN-RELECT

Identificador del acuerdo de subvención: 101160314

DOI

10.3030/101160314

Fecha de la firma de la CE 29 Abril 2024

Fecha de inicio 1 Octubre 2024

Fecha de finalización 30 Septiembre 2027

Financiado con arreglo a

• Widening participation and spreading excellence

Coste total

Sin datos

Aportación de la UE

€ 1 197 976,25

Coordinado por

PANEPISTIMIO THESSALIAS
Greece

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Publicaciones

Conference proceedings (12)

A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA

Autores: Giuseppe Chessa; Elena Bellodi; Michele Favalli; Davide Zoni; Davide Bertozzi
Publicado en: 2025 29th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2025, ISSN 2643-1483
Editor: IEEE
DOI: 10.1109/ASYNC65240.2025.00013

Prediction of Single Event Transient Propagation Using Machine Learning Models

Autores: Marko Andjelkovic, Junchao Chen, Jelisaveta Aleksic, Vishnu Padmakumar, Milos Marjanovic, Nikolaos Zazatis, Trupti Ranjan Lenka, Danijel Dankovic, Christos Sotiriou, Fabian Vargas
Publicado en: 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), 2025
Editor: IEEE
DOI: 10.1109/SMACD65553.2025.11092057

Compact SER Models via Model Order Reduction of Diffusion-Based Charge Collection

Autores: Pavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios-Ioannis Paliaroutis, George Floros
Publicado en: 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), 2025
Editor: IEEE
DOI: 10.1109/SMACD65553.2025.11092292

Design and Reliability Analysis of a Pipeline RISC-V Processor Core

Autores: Thiago H. Rausch, Wesley Grignani, Luigi Dilillo, and Douglas R. Melo
Publicado en: IEEE Latin-American Test Symp. (LATS), 2026, 2026
Editor: IEEE

Efficient TinyML Inference on a Fault-Tolerant RISC-V SoC with Vector Extension

Autores: Carolina Imianosky, Douglas A. Santos, Luigi Dilillo
Publicado en: 2025 10th International Workshop on Advances in Sensors and Interfaces (IWASI), 2025
Editor: IEEE
DOI: 10.1109/IWASI66786.2025.11121981

Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT)

Autores: Andjelkovic, Marko; Vargas, Fabian; Krstic, Milos; Dilillo, Luigi; Michez, Alain; Wrobel, Frederic; Bertozzi, Davide; Luján, Mikel; Georgakidis, Christos; Chatzivangelis, Nikolaos; Tsilingiri, Katerina; Zazatis, Nikolaos Zazatis; Paliaroutis, Georgios Ioanis; Tsoumanis, Pelopidas; Sotiriou, Christos
Publicado en: 2025 Design, Automation & Test in Europe Conference (DATE), 2025, ISSN 1558-1101
Editor: IEEE
DOI: 10.23919/DATE64628.2025.10992721

Post-Placement Timing Optimisations on Asynchronous Designs

Autores: Dimitrios Tsalapatas, Nikolaos Chatzivangelis, Christos P. Sotiriou, Nikolaos Sketopoulos
Publicado en: 2025 29th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2025
Editor: IEEE
DOI: 10.1109/ASYNC65240.2025.00025

Special Session Paper: Simulation Methodologies and Experiments for Reliability Analysis of Devices in Radiation Harsh Environments

Autores: Nikoloas Chatzivangelis, Nikoloas Zazatis, Wesley Grignani, Georgios-Ioannis Paliaroutis, Douglas A. Santos, Carolina Imianosky, Maria Kastriotou, Carlo Cazzaniga, Frédéric Wrobel, Alessandro Veronesi, Christos Sotiriou, Marko Andjelkovic, Fabian L. Vargas, Davide Bertozzi, Luigi Dilillo
Publicado en: 2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2025
Editor: IEEE
DOI: 10.1109/DFT66274.2025.11257502

Compact SER Models for Line-Source-Induced Charge Collection Using Model Order Reduction

Autores: Pavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios-Ioannis Paliaroutis, Luigi Dilillo, Anuj Pathania, George Floros
Publicado en: 2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2025
Editor: IEEE
DOI: 10.1109/DFT66274.2025.11257486

Characterization of a Fault-Tolerant RISC-V SoC in an SRAM-Based FPGA under Proton Irradiation

Autores: Wesley Grignani, Douglas A. Santos, Carolina Imianosky, Douglas R. Melo, Frédéric Wrobel, and Luigi Dilillo
Publicado en: IEEE Latin-American Test Symp. (LATS), 2026, 2026
Editor: IEEE

Resilience Analysis of a Fault-Tolerant MPSoC Interconnection Architecture under SEU Fault Injection

Autores: Douglas A. Santos, Wesley Grignani, Carolina Imianosky, Douglas R. Melo, and Luigi Dilillo
Publicado en: IEEE Latin-American Test Symp. (LATS), 2025, 2025
Editor: IEEE

Fault Injection Attacks Based on Layout-Driven SER Analysis

Autores: Alexandra Takou, Pelopidas Tsoumanis, Georgios-Ioannis Paliaroutis, Nestor Evmorfopoulos, George Stamoulis
Publicado en: 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), 2025
Editor: IEEE
DOI: 10.1109/SMACD65553.2025.11092174

Peer reviewed articles (3)

UPSET: A Comprehensive Probabilistic Single Event Transient Analysis Flow for VLSI Circuits Using Static Timing Analysis

Autores: Christos Georgakidis, Dimitris Valiantzas, Nikolaos Chatzivangelis, Marko Andjelkovic, Christos Sotiriou, Milos Krstic
Publicado en: Electronics, Edición 15, 2026, ISSN 2079-9292
Editor: MDPI AG
DOI: 10.3390/ELECTRONICS15040818

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Autores: Su, Zhe; Ramini, Simone; Coffen Marcolin, Demetra; Veronesi, Alessandro; Krstic, Milos; Indiveri, Giacomo; Bertozzi, Davide; Nowick, Steven M
Publicado en: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2024, ISSN 2156-3357
Editor: IEEE
DOI: 10.5167/UZH-268876

Efficient Reliability-Aware Hardware Trojan Design and Insertion for SET-Induced Soft Error Attacks

Autores: Alexandra Takou, Georgios-Ioannis Paliaroutis, Pelopidas Tsoumanis, Marko Andjelkovic, Fabian Vargas, Nestor Evmorfopoulos, George Stamoulis
Publicado en: Electronics, Edición 15, 2026, ISSN 2079-9292
Editor: MDPI AG
DOI: 10.3390/ELECTRONICS15020425