Periodic Reporting for period 1 - ViTFOX (Vision transformers with ferroelectric oxides)
Periodo di rendicontazione: 2024-10-01 al 2026-01-31
Horizon Europe Chips JU project ViTFOX bridges Europe and South Korea to build the next generation of AI-powered chips. The Transformer deep learning architecture has been successfully applied to the natural language processing (e.g. GPT). In ViTFOX, we aim to adapt and extend the transformer architecture to computer vision. It is foreseen that vision transformers (ViT) will replace convolutional neural networks (CNN) for image recognition because they could outperform CNN with 4 times fewer computing resources
In ViTFOX, the main target is to demonstrate one of the most important components of ViT, that is an analog compute-in-memory (CIM) unit using Si-compatible Haflia-based oxide ferroelectrics. For the implementation, two different device technologies will be employed: First a ferroelectric tunnel unction (FT) memristor technology driven by the EU part of the consortium, second, a ferroelectric random access memory (FeRAM) technology driven by the Korean part.
In brief, the high-level (system level) objectives are:
-Hardware-Software co-optimization for ViT with ferroelectric oxides expecting 30% energy improvement over DRAM
-Design circuit level simulator integrating: compact models of ferroelectric oxides, CMOS and peripherals targeting energy efficiency > 50 TOPS/Watt
-Design and fabrication of CIM demonstrator with a single layer network, sense amplifiers, logic controller
Two different implementations are envisaged with the aim to obtain energy efficiency >30 TOPS/W and accuracy >90%:
-32x32 arrays with epitaxial Ferroelectric Tunnel Junction (FTJ) synaptic weights,
-32x32 arrays with 1T-4C 3D FeRAM
The FTJ-based CIM will be monolithically integrated in the back-end of line (BEOL)of CMOS. To achieve this ambitious objective, the EU and Korean parts will tightly collaborate through the whole value chain from materials and devices to advanced processing and system design. The FeRAM will be fabricated separately and will be vertically stacked with CMOS. In parallel, the consortium in a proof-of-concept activity will heterogeneously integrate novel epitaxial ferroelectric synaptic devices by wafer bonding to identify major obstacles and show performance and yield.
In ViTFOX, the main target is to demonstrate one of the most important components of ViT, that is an analog compute-in-memory (CIM) unit using Si-compatible Haflia-based oxide ferroelectrics. For the implementation, two different device technologies will be employed: First a ferroelectric tunnel unction (FT) memristor technology driven by the EU part of the consortium, second, a ferroelectric random access memory (FeRAM) technology driven by the Korean part.
In brief, the high-level (system level) objectives are:
-Hardware-Software co-optimization for ViT with ferroelectric oxides expecting 30% energy improvement over DRAM
-Design circuit level simulator integrating: compact models of ferroelectric oxides, CMOS and peripherals targeting energy efficiency > 50 TOPS/Watt
-Design and fabrication of CIM demonstrator with a single layer network, sense amplifiers, logic controller
Two different implementations are envisaged with the aim to obtain energy efficiency >30 TOPS/W and accuracy >90%:
-32x32 arrays with epitaxial Ferroelectric Tunnel Junction (FTJ) synaptic weights,
-32x32 arrays with 1T-4C 3D FeRAM
The FTJ-based CIM will be monolithically integrated in the back-end of line (BEOL)of CMOS. To achieve this ambitious objective, the EU and Korean parts will tightly collaborate through the whole value chain from materials and devices to advanced processing and system design. The FeRAM will be fabricated separately and will be vertically stacked with CMOS. In parallel, the consortium in a proof-of-concept activity will heterogeneously integrate novel epitaxial ferroelectric synaptic devices by wafer bonding to identify major obstacles and show performance and yield.
A number of important accomplishments in materials, devices and system design tasks are a good step towards achieving the high level (system level) objectives. A brief account is given below:
Design of an energy-/accuracy-optimized CIM system targeting BNNs (ADC-less architecture) has been completed. We designed a novel training /inference method for crossbar-based BNNs, which has been successfully verified on CNN-based backbones (showing accuracy and energy improvement) and is currently being extended to ViT models with FeRAM/FTJ arrays.
Design of CMOS peripheral circuitry emulating neurons in binary weighted NN (BWNN) with FeRAM array has been completed and sent out to a foundry for fabrication using 0.5 μm technology CMOS MPW chip. Currently, a vertical stacking process is underway to integrate the FeRAM array on top of the fabricated 0.5 μm CMOS MPW chip. To test the vertically stacked FeRAM array with CMOS peripheral circuits, Software and hardware are both being developed to be used in a test platform based on a Tektronix pattern generator and an Agilent logic analyzer for array driving and operation verification
A microcontroller platform based on the Neuroboard prototype has been designed, fabricated and tested. The work focused on the first bring-up and initial characterization of the NeuroBoard prototype. The fabricated board was assembled and subject to electrical validation. Power-up tests confirmed correct startup behavior and initial measurements verified that the on-board DC/DC converters and voltage regulation stages deliver the expected supply rails. These tests establish that the board is operational at the power distribution level and provide a stable foundation for subsystem validation. After full validation of the platform, we aim to demonstrate that the FTJ-based CIM unit can execute analog vector matrix multiplication (VMM) and multiply and accumulate (MAC) which is at the heart of transformer neural network operation.
New ferroelectric/functional bottom electrode combinations were identified which are compatible with BEOL processing. Ferroelectric capacitors show non-volatile memcapacitive effects with zero static power consumption and very good retention, These devices could potentially emulate both synapses and neuron functionalities opening new opportunities for integrated neuromorphic computing technologies. The new materials and devices are good option for monolithic integration in the BEOL of CMOS.
Using suitable textured bottom electrodes and advanced fast (millisecond) annealing, Hafnia-based ferroelectric capacitors were obtained with significantly improved performance (speed and low voltage/power operation) and reliability. The high performance capacitors will be used in the FeRAM-based CIM array.
Design of an energy-/accuracy-optimized CIM system targeting BNNs (ADC-less architecture) has been completed. We designed a novel training /inference method for crossbar-based BNNs, which has been successfully verified on CNN-based backbones (showing accuracy and energy improvement) and is currently being extended to ViT models with FeRAM/FTJ arrays.
Design of CMOS peripheral circuitry emulating neurons in binary weighted NN (BWNN) with FeRAM array has been completed and sent out to a foundry for fabrication using 0.5 μm technology CMOS MPW chip. Currently, a vertical stacking process is underway to integrate the FeRAM array on top of the fabricated 0.5 μm CMOS MPW chip. To test the vertically stacked FeRAM array with CMOS peripheral circuits, Software and hardware are both being developed to be used in a test platform based on a Tektronix pattern generator and an Agilent logic analyzer for array driving and operation verification
A microcontroller platform based on the Neuroboard prototype has been designed, fabricated and tested. The work focused on the first bring-up and initial characterization of the NeuroBoard prototype. The fabricated board was assembled and subject to electrical validation. Power-up tests confirmed correct startup behavior and initial measurements verified that the on-board DC/DC converters and voltage regulation stages deliver the expected supply rails. These tests establish that the board is operational at the power distribution level and provide a stable foundation for subsystem validation. After full validation of the platform, we aim to demonstrate that the FTJ-based CIM unit can execute analog vector matrix multiplication (VMM) and multiply and accumulate (MAC) which is at the heart of transformer neural network operation.
New ferroelectric/functional bottom electrode combinations were identified which are compatible with BEOL processing. Ferroelectric capacitors show non-volatile memcapacitive effects with zero static power consumption and very good retention, These devices could potentially emulate both synapses and neuron functionalities opening new opportunities for integrated neuromorphic computing technologies. The new materials and devices are good option for monolithic integration in the BEOL of CMOS.
Using suitable textured bottom electrodes and advanced fast (millisecond) annealing, Hafnia-based ferroelectric capacitors were obtained with significantly improved performance (speed and low voltage/power operation) and reliability. The high performance capacitors will be used in the FeRAM-based CIM array.
The design and fabrication of a CIM consisting of 32x16 2T-2C FeRAM arrays integrated with CMOS peripheral circuits emulating neurons. Once the test platform is ready for CIM driving and operation verification, the consortium is expected to be able to show state of the art binary-weighted neural network results.
The identification of suitable ferroelectric synaptic devices compatible with BEOL processing is a big step forward and has a potential impact. To show the impact we first need to integrate the new ferroelectric devices in the BEOL of CMOS in the form of 32 x32 synaptic arrays to demonstrate a functional CIM unit capable of executing MAC operations. Next we plan to valorize and upscale our technology in a more industrial environment using the CHIPS JU pilot lines which is the most important step towards commercialization.
The identification of suitable ferroelectric synaptic devices compatible with BEOL processing is a big step forward and has a potential impact. To show the impact we first need to integrate the new ferroelectric devices in the BEOL of CMOS in the form of 32 x32 synaptic arrays to demonstrate a functional CIM unit capable of executing MAC operations. Next we plan to valorize and upscale our technology in a more industrial environment using the CHIPS JU pilot lines which is the most important step towards commercialization.