Final Report Summary - MICRO-IMU (MEMS-Accelerometer Miniaturisation of the analogue electronics in an Application Specific Circuit (ASIC))
Executive Summary:
One of the main goals of the Clean Sky Joint Undertaking (CSJU) is to speed up new aviation designs to protect our environment. This requires a complex innovation of all parts of the airplane. For instance, very small inertial measurement units (IMU) are necessary for the measurement of the aircraft wing deformation during flight. For this purpose, highly integrated sensor systems are needed. The goal for GEMAC/AMAC was the integration of the analogue part of a MEMS based accelerometer into an ASIC to reduce size and power consumption as much as possible and to fulfil the overall system requirements.
The MEMS based accelerometer consists of the sub-blocks high performance switches, charge amplifier, temperature probe, gain and offset, integrated 14-bit-ADC and voltage reference.
After a deep analysis of the system requirements and the capabilities of existing technologies, the XH035 CMOS technology from XFAB was selected for the ASIC manufacturing. After refinements of project planning and specification the design process started. To minimise the design risk, two preparations were planned. The first ASIC contains only the main components of the analogue part of the MEMS accelerometer, the switches ("ASIC A1"). Additionally, another main block was integrated in a separate test chip, the charge amplifier. In parallel to the fabrication phase of ASIC A1, the design, simulation, layout generation of the remaining blocks for the accelerometer system to be integrated in the final ASIC ("ASIC C") as well as the system integration of this ASIC started.
In March 2016 the ASIC department of GEMAC, the only partner in the Micro-IMU project (single submission) was outsourced into a new company, the "AMAC ASIC- und Mikrosensoranwendung Chemnitz GmbH". The project was transferred to AMAC in form of a PTRO (Partial Transfer of Rights and Obligations). Due to administrative reasons, especially the XFAB order, this resulted in a delay of the first preparation (ASIC A1 and test chip) and a modification of the project planning.
After delivery from XFAB the ASICs were tested. Except one parameter of ASIC A1, both ASICs have the requested functionality. The problem was the power consumption. ASIC A1 works only up to a voltage of +/-7V correctly. When operating with a voltage of +/-9V (as specified) the power consumption exceeds the specified value. After a complex failure analysis, parasitic effects in the layout were detected as reason. Complex design measures were taken to overcome the problem. Because a part of the wafers had been stopped it was possible to modify the layout on metal mask level and to continue the fabrication of this batch with a modified layout. However, not all modifications could be implemented. That's why the modified ASIC A1 did not meet the specification, too. The full set of modifications was implemented in the layout of ASIC C. Unfortunately, a fabrication problem arose in the fab. This caused a delay in the supply of ASIC C. Because a prolongation of the Micro-IMU project was not possible, the ASIC C will be tested now at AMAC after the official project end at own expense. It shall be guaranteed, that the CSJU partner SAFRAN will get the needed ASICs for industrialisation. In this way it will be possible to meet not only the scientific, but also the economic objectives of the project.
AMAC will replicate the acquired know-how for sophisticated analogue designs in other customer projects and for the development of own products. This will improve the market position of AMAC. In case of a correctly working ASIC C, a direct economic benefit will result from the purchase of ASICs to SAFRAN.
Because of the special characteristic of the project (single submission), dissemination activities were not planned. Publications and other dissemination activities will be made by the members of the Cleansky consortium.
Project Context and Objectives:
One of the main goals of the Clean Sky Joint Undertaking (CSJU) is to speed up new and greener aviation designs to protect our environment. Aircrafts have a 30-year service life, and it takes normally more than a decade to develop a new one. Clean Sky offers an accelerated research process to support the effective introduction of green technologies into aviation.
CSJU contributes with its results to achieve the technology breakthroughs that are necessary to make major steps towards the environmental goals sets by ACARE - Advisory Council for Aeronautics Research in Europe - the European Technology Platform for Aeronautics & Air Transport and to be reached in 2020:
• 50% reduction of CO2 emissions through drastic reduction of fuel consumption
• 80% reduction of NOx (nitrogen oxide) emissions
• 50% reduction of external noise
• A green product life cycle: design, manufacturing, maintenance and disposal / recycling
One of the strategic goals of the EC is to integrate also SMEs into the Cleansky projects to benefit from the know-how and flexibility of these companies, but also to offer them exceptional possibilities to enter the aircraft market and to find partners for further collaboration, which is otherwise very complicated for a SME.
These opportunities offered by Cleansky were the motivation for GEMAC as a typical SME with about 100 employees to apply for a challenging ASIC development project within CSJU. The ASIC designers of GEMAC had more than 20 years experiences in digital, analogue and mixed signal ASIC design, e.g for applications in the aviation/aeronautics field. In this way, GEMAC had the necessary qualifications to achieve the expected technical results of the project. In March 2016, GEMAC's ASIC department being responsible for the work within the Micro-IMU project was outsourced into a new company named "AMAC ASIC- und Mikrosensoranwendung Chemnitz GmbH". Because all engineers involved in the project switched to AMAC, the Micro-IMU project was completely transferred from GEMAC to AMAC in form of a Partial transfer of Rights and Obligations (PTRO).
For the measurement of the aircraft wing deformation during flight very small inertial measurement units (IMU) are necessary to make them suitable for integration into the wings of an airplane. This objective requires highly integrated sensor systems. Therefore, the goal for GEMAC/AMAC was the integration of the analogue part of the MEMS based accelerometer to be developed in CleanSky into an ASIC. This was the only way to reduce size and power consumption as much as possible and to fulfil the overall system requirements.
The MEMS based accelerometer consists of the following sub-blocks which were specified more detailed after first investigations (see attached Fig. 1):
1. High performance switches
2. Charge amplifier
3. Temperature probe
Measurement of the ASIC chip temperature (PTAT, integrated in ASIC)
An additional external probe must be added to the system to measure the MEMS sensor element temperature directly, not overlaid by temperature deviations caused by the self-heating of the ASIC
4. Gain and Offset
In dependency of sensor parameters, its functionality can be realized by the charge amplifier. If an external ADC is used, the Gain and Offset block adapts the signals to the input range of this ADC.
5. Integrated ADC (14 bit resolution)
The charge amplifier (block 2) must comply with the input requirements of the integrated ADC,
optionally an external ADC can be used.
6. Voltage reference
Supply of the programmable voltage references for the switches and the ground potential. The output voltage references are derived from the internal bandgap or are supplied by an external reference circuit (higher precision and stability).
The goal was to integrate as much as possible of these blocks into the ASIC, but in any case, the blocks 1-3.
In order to meet these objectives, the project work started with a deep analysis of the system to be integrated in order to get the necessary information for the technology selection and to evaluate the main parameters, e.g. time restrictions or functional challenges. A refinement of the project planning followed this step. After an analysis of feasibility and existing risks as well as a cost estimation for the possible technologies together with our Cleansky partner SAFRAN, a CMOS technology of manufacturer XFAB was selected and the design work started. To minimise risks it was decided to modify the original workflow: In a first step an ASIC was designed and manufactured which contains only the main components of the analogue part of the MEMS accelerometer: the switches ("ASIC A1"). After successful testing, it was the objective to implement this part into a second and more complex "ASIC C" having the complete functionality and consisting of all blocks 1-7 (see above). The final objective was to integrate the ASICs into the MEMS based accelerometer system of SAFRAN. For this purpose, it was planned to test the ASICs in two steps: stand-alone and system- integrated.
Because of the special characteristic of the project (single submission), dissemination activities were not planned within the project. The ASIC will be supplied to the CSJU project partner SAFRAN who will implement them into the more complex MEMS based accelerometer system and later into the airplane. Publications and other dissemination activities will be made by the members of the Cleansky consortium.
Project Results:
In this section the main scientific and technical results will be described in line with the working package structure of the DoW.
1. WP1: Specification and feasibility analysis
The first task within this workpackage was the analysis and evaluation of the ASIC requirements in regard to their realisation possibilities in different ASIC technologies. This step was important for both the technical and also for the economic aspects of the project. Therefore, the CSJU partner SAFRAN was always involved in the technology selection process.
Available CMOS / BiCMOS (Si, GeSi,...) or bipolar technologies for ASICs do not provide gate oxide thicknesses which withstand voltages larger than about 20V. Comparing XFAB technologies with competing technologies, XFAB's technologies are placed in the upper area. The goal was to use a standard technology, because the development of special technology options would have been in principle possible with fab assistance, but due to the costs and the necessary development time (on average more than one year) this way was not a realistic alternative for the Micro-IMU project.
In the beginning, also an alternative was discussed: the development and manufacturing of the ASIC in a special technology, e.g. VMOS. However, these technologies are not available for ASIC customers on the market, because the manufacturers (e.g. Analog Devices, STMicroelectronics) do not offer these technologies for design houses except for special cases with very high production volumes.
As a result of the feasibility analysis, two possible ASIC technologies were selected, and the compliance matrix defined by SAFRAN was updated and agreed:
a) XFAB CMOS technology XH035 (minimum structure width 0.35μm)
The XH035 series is X-FAB’s 0.35-micron Modular RF capable Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for industrial, automotive and telecommunication products. Based on a single poly, triple metal 0.35-micron drawn gate length process for digital applications, process modules are available such as embedded Non-Volatile Memory, high voltage options, as well as standard or thick fourth layer metal, double-poly and MIM capacitor and high resistance polysilicon. Bipolar as well as MOS Transistors are available. Worldclass low noise p-mos and n-mos transistors make this technology a first choice for application needing very low noise and high signal-to-noise ratios. All main modules are comparable in Design Rules and Transistor Performance with other state of the art 0.35μm CMOS Processes
Important key features:
0.35-micron single poly, triple metal CMOS basic process with modular concept
3.3V Core, 5V tolerant I/O
5V dual gate or 5V only module
Low threshold voltage option
Low leakage process option
Four layer metal options for high density circuits
Thick top metal for inductors and Smart Power applications
Benchmark setting Low noise p-mos and n-mos transistors
Polyimide module for stress relief & passivation protection
High density up to 28000 gates per mm2
I/O cell library with 4kV HBM ESD protection levels
Typical ad worst-case models - BSIM3v3.24 (MOS, BJT, RES, CAP)
MOS 1/f noise characterized & included in model
Operating Conditions: Tj = -40ºC ... +125ºC
b) SOI technology XT018 (minimum structure width 0.18μm).
The XH018 series is X-FAB’s 0.18 micron Modular Mixed Signal HV CMOS Technology. Based upon the industrial standard single poly with up to six metal layers 0.18 micron drawn gate length N-well process, integrated with high-voltage and Non-Volatile-Memory modules, the platform is ideal for SOC applications in the automotive market, as well as embedded high-voltage applications in the communications, consumer and industrial market.
Important key features:
• 0.18-micron single poly, up to six-metal N-well CMOS basic process
• Modular concept
• Up to 175ºC operating temperature, extending beyond AEC Q100 requirement
• Low Power core module
• Thick metal layers optional module
• Integrated digital, analog, HV and NVM in a single process
• Isolation well for all 1.8V 3.3V and 40V MOS devices
• Excellent Ron in HVMOS module with multiple resurf technology
• 10-45V sym./asy. HVMOS transistors
• 35-45V DMOS transistors
• Vertical NPN BJT
• ESD protected HV PNP for reverse polarity protection (e.g. for LIN pins)
• Low noise PMOS transistors
• Low Vt Transistors
• Integrated high-ohmic poly resistor in core module (zero mask penalty)
• High capacitance single, double, triple MIM and fringe capacitors
• High density up to 125000 gates per mm2
The CMOS technology XH018 as an alternative for the XH035 technology wasn't a real, because this technology offers no additional advantages. It is more expensive and the maximum voltage rates of its primitive devices are lower.
For the technology selection process designs of several ASIC components were realised in these two technologies, and the results were evaluated.
a) Power supply
In both technologies, the voltages
• ±30 V,
• ±VDDA,
• 0V and
• 3.3V
have to be provided externally. Both technologies are not bipolar. Thus, the lowest voltage -30V has to be connected to substrate. Figure 2 (see Annex) illustrates the power supply complex with the resulting internal voltages (red) in respect to the substrate.
In the XH035 technology the analogue voltage supply (±VDDA) must have a value of ±1.65V in the XT018 technology ±2.5V.
Apart from the common placing of transistors in tubs in CMOS technology, in case of multi supply applications in XH035 technology additional tubs for the circuits are necessary in order to isolate the circuits from the substrate. The tub isolation is made by p/n junctions, which are polarized in blocking direction. In SOI technology this isolation is made by oxide. This is a great advantage because this isolation is independent of voltage and polarization.
In respect to different power supplies, the SOI process offers in general more degrees of freedom for the design, but the fabrication costs are higher.
b) Bandgap
For both technologies the cells were designed in a similar architecture. There are no significant differences in the simulation results.
c) Switch (DAC, Mux)
The switches are necessary to excite the outer sensor electrodes and are the most important part of the ASIC. That's why different design approaches were realised in both technologies. After complex simulations of all these alternative versions, the best one was used for the direct comparison of the two favoured technologies.
The voltage has to be switched between ±Vref and also to 0V. Challenges for the design were the voltage range, the switching time and the ON-resistance of the switches. Furthermore, the switch for providing 0V was difficult to realize in CMOS bulk or SOI technology. Independent of the used MOS transistors this switch opens backward in dependency of the voltage of the outer sensor electrodes. To avoid that, a special circuit was developed to keep the transistor source and gate potential at the lowest (for p channel transistor highest) voltage level, if the switch has to be high resistive. Special measures had to be taken that the maximum gate bulk voltage does not exceed 18V.
In order to save area and to achieve low C- and Ron values and herewith to short switching times, the architecture of the functional unit DAC / MUX was slightly modified. All excitation combinations for the sensor can be realized now with the modified circuit. Figure 3 (see Annex) shows the block structure of the switch unit.
d) Operational Amplifier
For both technologies different architectures for Operational Amplifiers were investigated. For high gain bandwidth OpAmps input stages with bipolar transistors are the normally preferred solution, but due to their input current they are not suitable for charge amplifiers.
Due to differences between XH035 and SOI technologies the designs of the OpAmps are different.
Structure of OpAmp in XH035:
• pmos differential stage
• push pull output stage consisting of npn bipolar and nmos transistor
• Supply: ±1.65 V (3.3V)
• Output voltage swing: ±1 V
Structure of OpAmp in XT018:
• nmos differential stage
• push pull output stage consisting of pnp bipolar and jpmos transistor
• Supply: ±2.5 V (5 V)
• Output voltage swing: ±2 V
The next step was the analysis of the recurring and non-recurring costs for series ASIC production in the two potential ASIC technologies assuming a demand of 600, 2000 or 6000 ASICs per year. Comparing the 600 and 6000 unit alternatives, a cost reduction of about 50% is possible. The price range varies between 13,20€ and 6.60€ per ASIC for XH035 and 16,70€ and 8,40€ for XT018 technology. The cost estimation refers to the complete ASIC (i.e. not only switches).
The following table gives a comparing overview for both technologies:
XH035 XT018
Costs lower High non recurrent costs
Power Supply only ±1.65 analogue power supply ±2.5 analogue power supply; isolation by oxide for more robustness
Performance bandgap similar
Performance DAC / MUX Slope, Ron of high- and low side switches are similar
Lower Ron of Switch to zero
Size for DAC / MUX About half the size of power devices
Performance Operational Amplifier Similar; The maximum slew rate is a problem.
The results show that the ASIC can be realised with similar properties in both technologies. The selection of technology depends on the weighting of parameters and costs. Finally, regarding both the technological and economic features, SAFRAN and GEMAC selected the XH035 technology for ASIC realisation.
Based on the results of WP1, and after intensive discussions with SAFRAN a positive Go-Ahead decision was made, i.e. the first milestone was reached with positive results.
2. WP2: Refinement of project planning
To minimise the design risks, different preparation strategies were discussed with SAFRAN. The following strategy was agreed for both ASIC runs (ASIC A1 and C). The workplan was modified accordingly.
First Preparation:
• Manufacturing of two ASICs for test purposes ( A1 ASIC with different switch designs; one test-chip with charge amplifier)
• Manufacturing of six wafers, three of them stopped before process step "poly"
. ASIC test by GEMAC and SAFRAN
• If necessary: correction of masks for special kinds of failures.
• Continued preparation of three stopped wafers with modified masks for the following process steps, including poly deposition
In this way, it was possible to accelerate the implementation of necessary modifications, because for a special group of failures a complete new run became unnecessary by mask corrections. This saved time and allowed the introduction of a second test phase for the A1 ASICs of the first preparation.
Second preparation:
• Similar strategy as preparation 1: MPW, six wafers, three stopped before poly.
• Preparation of two ASICs:
- modified ASIC A1 (if necessary)
- ASIC C (complete system with all blocks – see Annex, Fig.1)
3. WP3: Architectural design
Based on the feedback of the specification analysis (WP1) and the results of the feasibility investigations, the specifications were updated and refined regarding the target parameters of the ASIC, the external and internal (i.e. between the blocks) interfaces and timing conditions. In order to check the system functionality, first designs for the functional blocks were done within this workpackage. The following blocks had to be realised:
- 4 independent single-pole, single-throw switches
- DAC + MUX
- Charge amplifier
- ADC (along with gain and offset adaptation stage)
- Thermal probe
- Voltage references
ASIC A1
This ASIC contains only the switches.
ASIC A1 was used to evaluate performances of a DAC+MUX function on SAGEM’s evaluation boards. It offers the possibility to work either with one single switch, or to wire all switches to one system. Fig.4 (see Annex) shows the functional block diagram of ASIC A1. The four switches are totally independent (except for power supplies PVREF, MVREF and DGND, and voltage VLOGIC).
For the ASIC integration a premoulded Narrow SOIC 16 package was selected.
ASIC C
ASIC C contains all functional blocks. It is the basis for the later series version, and is used for the test of the global behaviour and performance.
The DAC and MUX functions which are critical parts of the analogue chain are implemented in the ASIC which will drive the MEMS sensor of the accelerometer. It also processes the MEMS output with a charge amplifier and an ADC. The ADC is preceded by an adaptation stage (in gain and/or offset) to obtain the best range and performances of the ADC.
Voltage references PVREF and MVREF are synthesized by the ASIC itself from a VREF_IN external signal (band-gap or similar). Large external decoupling capacitors are used.
ASIC_C embeds also a digital thermal probe. Additionally, a 14-Bit-Analog-to-Digital-Converter is implemented in ASIC C. It performs 12-bit true analogue to digital conversion of the charge amplifier full-scale range. ASIC C is packaged into a PLCC68 package.
4. WP4/WP5: ASIC Design and Manufacturing / Full ASIC Design
The simulation results of the A1 ASIC including back annotation simulation on layout basis were discussed intensively with SAFRAN. After the design release the manufacturing process started at XFAB. Fig. 6 (see Annex) shows the final ASIC layout.
Within the first Multi Layer Mask Run, two types of ASICs were prepared. The first ASIC (ASIC A1) contains the switches according to the specification of SAFRAN. The second one contains the charge amplifier being part of ASIC C, which was prepared for test purposes.
The originally planned ASIC A2 became obsolete, because the A1 ASIC offers the possibility to work either with one single switch, or to wire all switches to one system. The pinning of both ASICs is identical.
The necessary test boards for both ASICs were designed in parallel to the XFAB fabrication process.
After delivery from XFAB the ASICs were tested. Except one parameter of ASIC A1, both ASICs have the requested functionality. The problem was the power consumption. ASIC A1 works only up to a voltage of +/-7V correctly. When operating with a voltage of +/-9V (as specified) the power consumption exceeds the specified value. After a complex failure analysis, parasitic effects in the layout were detected as reason. Complex design measures were taken to overcome the problem. Because a part of the wafers had been stopped, it was possible to modify the layout on metal mask level and to continue the fabrication of this batch with a modified layout. However, not all modifications could be implemented on metal mask level. That's why remained a design risk. Finally, the modified ASIC A1 did not meet the specification, too.
The complete set of modifications resulting from the failure analysis for ASIC A1 (see Deliverables 4.3 and 4.4) were implemented into the layout of ASIC C. Especially, this concerned all modifications to prevent the parasitic effects. The charge amplifier layout was implemented without modifications. This block works as specified.
ASIC C contains the following main blocks:
• DAC/MUX unit with high performance switches (fully modified according to test results of ASIC A1)
The main components of the DAC and MUX block are the switches. It must be noted that the switches are not simple sub-blocks. With respect to the planned application in avionics, the requirements regarding parameter values (e.g. fall and rise times), stability, power consumption and reliability are highly demanding and bring the CMOS technology to its limits. To meet the specification, a lot of special design measures were necessary which made the design process very complex and time-consuming.
For the several needed supply voltages, tailored transistors with specific characteristics had to be designed and were implemented into the switches. This was the only way to guarantee a stable and equal behaviour for the whole voltage range.
• Charge Amplifier (successful tested version)
The function of the charge amplifier is to measure the modulated charges during detection phases without significant alteration of the wave shapes applied to the electrodes. For the realisation of the charge amplifier different designs were made and simulated. The final version of this block was integrated in a separate test chip. This intermediate step was necessary, because the requested values for bandwidth, voltage swing and settling time are critical parameters.
• Thermal probe
The thermal probe is used for measuring the precise chip temperature. The value is digitalised and stored in a register. Via Interface 2 this register can be read. Two measurement ranges are selectable. According to the specification, the temperature range to be measured is between -55°C and +110°C.
• Integrated A/D Converter
Basis for development of the Analogue to Digital Converter was AMACs own 14bit-ADC (IP block). For the Micro-IMU project it was modified. To comply with the timing requirements and the resolution of true 12 bits, a resolution of 13 bits was calculated.
• Voltage reference
The reference block is another main block of ASIC C. Very high precise voltage references are essential for the operation of both ADCs, the charge amplifier and temperature probe. All internal references and also the voltages MVREF and PVREF are derived from an external reference voltage cell. An external reference source is used because of its better parameters compared to an integrated solution. Furthermore, the derived voltages can be trimmed via the serial interface to compensate offset errors of the amplifiers. As example, Figure 5 shows the effect of modifying the adjustment registers of the upper and lower ADC reference voltage at different temperatures. The normal values are + 500mV for the upper and -500mV for the lower reference. They can be modified in steps of 3.1 mV over a range of +/- 25mV.
The voltages PVREF (+9V) and MVREF (-9V) are also adjustable over a range of 80mV in steps of 5mV.
The originally planned On-chip diagnostic components were not implemented, because all critical points of the circuit can be directly accessed via the ASIC pins.
ASIC C has two interfaces for communication. Because of the high data rates and the real time computing, the Serial Interface 1 is only used for the transmission of the acceleration data. Interface 2 serves for the read out of the measured temperature, and for writing the configuration and adjustment register. To avoid influences between the ADCs, each one has its own references, which can be trimmed separately.
The positive and negative reference voltage of each converter cannot be adjusted separately, because an exact reference voltage range is the most important condition for the correct operation of the ADC (and not its exact limit values).
The basis for the final layout was the developed floorplan (see Annex, Fig. 6). Main criteria to be considered in the design were
• freedom from interferences between the different blocks
• different voltage levels of the blocks
• positions of the pads, especially for the sensor element.
All interface pins are placed on the “east side” of the layout, sensitive analogue ones are not arranged here. The control signals for the switches are on the “west side”. The sensitive charge amplifier pads are located altogether in the north. The TBD marked pads in the floorplan were placed only for reserve purposes in the design phase and don’t have corresponding pads in the layout.
Fig. 7 in the Annex shows the final layout. The resulting behaviour was checked by complex back-annotation simulations.
ASIC C has a size of 4.15 x 3.35 mm² and 51 pads. For testing it will be housed into a CLCC 68 package (ceramic leaded chip carrier).
Because of delays in the manufacturing process for ASIC A1 resulting from the PTRO (Partial Transfer of Rights and Obligations) from GEMAC to AMAC, the time-consuming failure analysis to find the reasons for the parasitic effects and problems in the fabrication process of XFAB it was not possible to test the delivered ASIC C prototypes within the Micro-IMU project. It will be done by AMAC after the official project end at own expense.
The objective is to deliver ASIC C prototypes with full functionality to our CSJU partner SAFRAN in May/June 2017 for a complex system test, and to start the industrialisation process.
Potential Impact:
AMAC will replicate the acquired know-how for sophisticated analogue designs in other customer projects and for the development of own products. This will improve the market position of AMAC and will safeguard the employment in the company.
In case of a correctly working ASIC C, a direct economic benefit will result from the purchase of ASICs to SAFRAN.
Because of the special characteristic of the project (single submission), dissemination activities were not planned. The benefits and potential impact of the developed ASIC can be demonstrated only in the context of the complete MEMS based accelerometer system. Therefore, publications and other dissemination activities will be made by the members of the Cleansky consortium. AMAC will assist if required.
List of Websites:
not applicable
One of the main goals of the Clean Sky Joint Undertaking (CSJU) is to speed up new aviation designs to protect our environment. This requires a complex innovation of all parts of the airplane. For instance, very small inertial measurement units (IMU) are necessary for the measurement of the aircraft wing deformation during flight. For this purpose, highly integrated sensor systems are needed. The goal for GEMAC/AMAC was the integration of the analogue part of a MEMS based accelerometer into an ASIC to reduce size and power consumption as much as possible and to fulfil the overall system requirements.
The MEMS based accelerometer consists of the sub-blocks high performance switches, charge amplifier, temperature probe, gain and offset, integrated 14-bit-ADC and voltage reference.
After a deep analysis of the system requirements and the capabilities of existing technologies, the XH035 CMOS technology from XFAB was selected for the ASIC manufacturing. After refinements of project planning and specification the design process started. To minimise the design risk, two preparations were planned. The first ASIC contains only the main components of the analogue part of the MEMS accelerometer, the switches ("ASIC A1"). Additionally, another main block was integrated in a separate test chip, the charge amplifier. In parallel to the fabrication phase of ASIC A1, the design, simulation, layout generation of the remaining blocks for the accelerometer system to be integrated in the final ASIC ("ASIC C") as well as the system integration of this ASIC started.
In March 2016 the ASIC department of GEMAC, the only partner in the Micro-IMU project (single submission) was outsourced into a new company, the "AMAC ASIC- und Mikrosensoranwendung Chemnitz GmbH". The project was transferred to AMAC in form of a PTRO (Partial Transfer of Rights and Obligations). Due to administrative reasons, especially the XFAB order, this resulted in a delay of the first preparation (ASIC A1 and test chip) and a modification of the project planning.
After delivery from XFAB the ASICs were tested. Except one parameter of ASIC A1, both ASICs have the requested functionality. The problem was the power consumption. ASIC A1 works only up to a voltage of +/-7V correctly. When operating with a voltage of +/-9V (as specified) the power consumption exceeds the specified value. After a complex failure analysis, parasitic effects in the layout were detected as reason. Complex design measures were taken to overcome the problem. Because a part of the wafers had been stopped it was possible to modify the layout on metal mask level and to continue the fabrication of this batch with a modified layout. However, not all modifications could be implemented. That's why the modified ASIC A1 did not meet the specification, too. The full set of modifications was implemented in the layout of ASIC C. Unfortunately, a fabrication problem arose in the fab. This caused a delay in the supply of ASIC C. Because a prolongation of the Micro-IMU project was not possible, the ASIC C will be tested now at AMAC after the official project end at own expense. It shall be guaranteed, that the CSJU partner SAFRAN will get the needed ASICs for industrialisation. In this way it will be possible to meet not only the scientific, but also the economic objectives of the project.
AMAC will replicate the acquired know-how for sophisticated analogue designs in other customer projects and for the development of own products. This will improve the market position of AMAC. In case of a correctly working ASIC C, a direct economic benefit will result from the purchase of ASICs to SAFRAN.
Because of the special characteristic of the project (single submission), dissemination activities were not planned. Publications and other dissemination activities will be made by the members of the Cleansky consortium.
Project Context and Objectives:
One of the main goals of the Clean Sky Joint Undertaking (CSJU) is to speed up new and greener aviation designs to protect our environment. Aircrafts have a 30-year service life, and it takes normally more than a decade to develop a new one. Clean Sky offers an accelerated research process to support the effective introduction of green technologies into aviation.
CSJU contributes with its results to achieve the technology breakthroughs that are necessary to make major steps towards the environmental goals sets by ACARE - Advisory Council for Aeronautics Research in Europe - the European Technology Platform for Aeronautics & Air Transport and to be reached in 2020:
• 50% reduction of CO2 emissions through drastic reduction of fuel consumption
• 80% reduction of NOx (nitrogen oxide) emissions
• 50% reduction of external noise
• A green product life cycle: design, manufacturing, maintenance and disposal / recycling
One of the strategic goals of the EC is to integrate also SMEs into the Cleansky projects to benefit from the know-how and flexibility of these companies, but also to offer them exceptional possibilities to enter the aircraft market and to find partners for further collaboration, which is otherwise very complicated for a SME.
These opportunities offered by Cleansky were the motivation for GEMAC as a typical SME with about 100 employees to apply for a challenging ASIC development project within CSJU. The ASIC designers of GEMAC had more than 20 years experiences in digital, analogue and mixed signal ASIC design, e.g for applications in the aviation/aeronautics field. In this way, GEMAC had the necessary qualifications to achieve the expected technical results of the project. In March 2016, GEMAC's ASIC department being responsible for the work within the Micro-IMU project was outsourced into a new company named "AMAC ASIC- und Mikrosensoranwendung Chemnitz GmbH". Because all engineers involved in the project switched to AMAC, the Micro-IMU project was completely transferred from GEMAC to AMAC in form of a Partial transfer of Rights and Obligations (PTRO).
For the measurement of the aircraft wing deformation during flight very small inertial measurement units (IMU) are necessary to make them suitable for integration into the wings of an airplane. This objective requires highly integrated sensor systems. Therefore, the goal for GEMAC/AMAC was the integration of the analogue part of the MEMS based accelerometer to be developed in CleanSky into an ASIC. This was the only way to reduce size and power consumption as much as possible and to fulfil the overall system requirements.
The MEMS based accelerometer consists of the following sub-blocks which were specified more detailed after first investigations (see attached Fig. 1):
1. High performance switches
2. Charge amplifier
3. Temperature probe
Measurement of the ASIC chip temperature (PTAT, integrated in ASIC)
An additional external probe must be added to the system to measure the MEMS sensor element temperature directly, not overlaid by temperature deviations caused by the self-heating of the ASIC
4. Gain and Offset
In dependency of sensor parameters, its functionality can be realized by the charge amplifier. If an external ADC is used, the Gain and Offset block adapts the signals to the input range of this ADC.
5. Integrated ADC (14 bit resolution)
The charge amplifier (block 2) must comply with the input requirements of the integrated ADC,
optionally an external ADC can be used.
6. Voltage reference
Supply of the programmable voltage references for the switches and the ground potential. The output voltage references are derived from the internal bandgap or are supplied by an external reference circuit (higher precision and stability).
The goal was to integrate as much as possible of these blocks into the ASIC, but in any case, the blocks 1-3.
In order to meet these objectives, the project work started with a deep analysis of the system to be integrated in order to get the necessary information for the technology selection and to evaluate the main parameters, e.g. time restrictions or functional challenges. A refinement of the project planning followed this step. After an analysis of feasibility and existing risks as well as a cost estimation for the possible technologies together with our Cleansky partner SAFRAN, a CMOS technology of manufacturer XFAB was selected and the design work started. To minimise risks it was decided to modify the original workflow: In a first step an ASIC was designed and manufactured which contains only the main components of the analogue part of the MEMS accelerometer: the switches ("ASIC A1"). After successful testing, it was the objective to implement this part into a second and more complex "ASIC C" having the complete functionality and consisting of all blocks 1-7 (see above). The final objective was to integrate the ASICs into the MEMS based accelerometer system of SAFRAN. For this purpose, it was planned to test the ASICs in two steps: stand-alone and system- integrated.
Because of the special characteristic of the project (single submission), dissemination activities were not planned within the project. The ASIC will be supplied to the CSJU project partner SAFRAN who will implement them into the more complex MEMS based accelerometer system and later into the airplane. Publications and other dissemination activities will be made by the members of the Cleansky consortium.
Project Results:
In this section the main scientific and technical results will be described in line with the working package structure of the DoW.
1. WP1: Specification and feasibility analysis
The first task within this workpackage was the analysis and evaluation of the ASIC requirements in regard to their realisation possibilities in different ASIC technologies. This step was important for both the technical and also for the economic aspects of the project. Therefore, the CSJU partner SAFRAN was always involved in the technology selection process.
Available CMOS / BiCMOS (Si, GeSi,...) or bipolar technologies for ASICs do not provide gate oxide thicknesses which withstand voltages larger than about 20V. Comparing XFAB technologies with competing technologies, XFAB's technologies are placed in the upper area. The goal was to use a standard technology, because the development of special technology options would have been in principle possible with fab assistance, but due to the costs and the necessary development time (on average more than one year) this way was not a realistic alternative for the Micro-IMU project.
In the beginning, also an alternative was discussed: the development and manufacturing of the ASIC in a special technology, e.g. VMOS. However, these technologies are not available for ASIC customers on the market, because the manufacturers (e.g. Analog Devices, STMicroelectronics) do not offer these technologies for design houses except for special cases with very high production volumes.
As a result of the feasibility analysis, two possible ASIC technologies were selected, and the compliance matrix defined by SAFRAN was updated and agreed:
a) XFAB CMOS technology XH035 (minimum structure width 0.35μm)
The XH035 series is X-FAB’s 0.35-micron Modular RF capable Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for industrial, automotive and telecommunication products. Based on a single poly, triple metal 0.35-micron drawn gate length process for digital applications, process modules are available such as embedded Non-Volatile Memory, high voltage options, as well as standard or thick fourth layer metal, double-poly and MIM capacitor and high resistance polysilicon. Bipolar as well as MOS Transistors are available. Worldclass low noise p-mos and n-mos transistors make this technology a first choice for application needing very low noise and high signal-to-noise ratios. All main modules are comparable in Design Rules and Transistor Performance with other state of the art 0.35μm CMOS Processes
Important key features:
0.35-micron single poly, triple metal CMOS basic process with modular concept
3.3V Core, 5V tolerant I/O
5V dual gate or 5V only module
Low threshold voltage option
Low leakage process option
Four layer metal options for high density circuits
Thick top metal for inductors and Smart Power applications
Benchmark setting Low noise p-mos and n-mos transistors
Polyimide module for stress relief & passivation protection
High density up to 28000 gates per mm2
I/O cell library with 4kV HBM ESD protection levels
Typical ad worst-case models - BSIM3v3.24 (MOS, BJT, RES, CAP)
MOS 1/f noise characterized & included in model
Operating Conditions: Tj = -40ºC ... +125ºC
b) SOI technology XT018 (minimum structure width 0.18μm).
The XH018 series is X-FAB’s 0.18 micron Modular Mixed Signal HV CMOS Technology. Based upon the industrial standard single poly with up to six metal layers 0.18 micron drawn gate length N-well process, integrated with high-voltage and Non-Volatile-Memory modules, the platform is ideal for SOC applications in the automotive market, as well as embedded high-voltage applications in the communications, consumer and industrial market.
Important key features:
• 0.18-micron single poly, up to six-metal N-well CMOS basic process
• Modular concept
• Up to 175ºC operating temperature, extending beyond AEC Q100 requirement
• Low Power core module
• Thick metal layers optional module
• Integrated digital, analog, HV and NVM in a single process
• Isolation well for all 1.8V 3.3V and 40V MOS devices
• Excellent Ron in HVMOS module with multiple resurf technology
• 10-45V sym./asy. HVMOS transistors
• 35-45V DMOS transistors
• Vertical NPN BJT
• ESD protected HV PNP for reverse polarity protection (e.g. for LIN pins)
• Low noise PMOS transistors
• Low Vt Transistors
• Integrated high-ohmic poly resistor in core module (zero mask penalty)
• High capacitance single, double, triple MIM and fringe capacitors
• High density up to 125000 gates per mm2
The CMOS technology XH018 as an alternative for the XH035 technology wasn't a real, because this technology offers no additional advantages. It is more expensive and the maximum voltage rates of its primitive devices are lower.
For the technology selection process designs of several ASIC components were realised in these two technologies, and the results were evaluated.
a) Power supply
In both technologies, the voltages
• ±30 V,
• ±VDDA,
• 0V and
• 3.3V
have to be provided externally. Both technologies are not bipolar. Thus, the lowest voltage -30V has to be connected to substrate. Figure 2 (see Annex) illustrates the power supply complex with the resulting internal voltages (red) in respect to the substrate.
In the XH035 technology the analogue voltage supply (±VDDA) must have a value of ±1.65V in the XT018 technology ±2.5V.
Apart from the common placing of transistors in tubs in CMOS technology, in case of multi supply applications in XH035 technology additional tubs for the circuits are necessary in order to isolate the circuits from the substrate. The tub isolation is made by p/n junctions, which are polarized in blocking direction. In SOI technology this isolation is made by oxide. This is a great advantage because this isolation is independent of voltage and polarization.
In respect to different power supplies, the SOI process offers in general more degrees of freedom for the design, but the fabrication costs are higher.
b) Bandgap
For both technologies the cells were designed in a similar architecture. There are no significant differences in the simulation results.
c) Switch (DAC, Mux)
The switches are necessary to excite the outer sensor electrodes and are the most important part of the ASIC. That's why different design approaches were realised in both technologies. After complex simulations of all these alternative versions, the best one was used for the direct comparison of the two favoured technologies.
The voltage has to be switched between ±Vref and also to 0V. Challenges for the design were the voltage range, the switching time and the ON-resistance of the switches. Furthermore, the switch for providing 0V was difficult to realize in CMOS bulk or SOI technology. Independent of the used MOS transistors this switch opens backward in dependency of the voltage of the outer sensor electrodes. To avoid that, a special circuit was developed to keep the transistor source and gate potential at the lowest (for p channel transistor highest) voltage level, if the switch has to be high resistive. Special measures had to be taken that the maximum gate bulk voltage does not exceed 18V.
In order to save area and to achieve low C- and Ron values and herewith to short switching times, the architecture of the functional unit DAC / MUX was slightly modified. All excitation combinations for the sensor can be realized now with the modified circuit. Figure 3 (see Annex) shows the block structure of the switch unit.
d) Operational Amplifier
For both technologies different architectures for Operational Amplifiers were investigated. For high gain bandwidth OpAmps input stages with bipolar transistors are the normally preferred solution, but due to their input current they are not suitable for charge amplifiers.
Due to differences between XH035 and SOI technologies the designs of the OpAmps are different.
Structure of OpAmp in XH035:
• pmos differential stage
• push pull output stage consisting of npn bipolar and nmos transistor
• Supply: ±1.65 V (3.3V)
• Output voltage swing: ±1 V
Structure of OpAmp in XT018:
• nmos differential stage
• push pull output stage consisting of pnp bipolar and jpmos transistor
• Supply: ±2.5 V (5 V)
• Output voltage swing: ±2 V
The next step was the analysis of the recurring and non-recurring costs for series ASIC production in the two potential ASIC technologies assuming a demand of 600, 2000 or 6000 ASICs per year. Comparing the 600 and 6000 unit alternatives, a cost reduction of about 50% is possible. The price range varies between 13,20€ and 6.60€ per ASIC for XH035 and 16,70€ and 8,40€ for XT018 technology. The cost estimation refers to the complete ASIC (i.e. not only switches).
The following table gives a comparing overview for both technologies:
XH035 XT018
Costs lower High non recurrent costs
Power Supply only ±1.65 analogue power supply ±2.5 analogue power supply; isolation by oxide for more robustness
Performance bandgap similar
Performance DAC / MUX Slope, Ron of high- and low side switches are similar
Lower Ron of Switch to zero
Size for DAC / MUX About half the size of power devices
Performance Operational Amplifier Similar; The maximum slew rate is a problem.
The results show that the ASIC can be realised with similar properties in both technologies. The selection of technology depends on the weighting of parameters and costs. Finally, regarding both the technological and economic features, SAFRAN and GEMAC selected the XH035 technology for ASIC realisation.
Based on the results of WP1, and after intensive discussions with SAFRAN a positive Go-Ahead decision was made, i.e. the first milestone was reached with positive results.
2. WP2: Refinement of project planning
To minimise the design risks, different preparation strategies were discussed with SAFRAN. The following strategy was agreed for both ASIC runs (ASIC A1 and C). The workplan was modified accordingly.
First Preparation:
• Manufacturing of two ASICs for test purposes ( A1 ASIC with different switch designs; one test-chip with charge amplifier)
• Manufacturing of six wafers, three of them stopped before process step "poly"
. ASIC test by GEMAC and SAFRAN
• If necessary: correction of masks for special kinds of failures.
• Continued preparation of three stopped wafers with modified masks for the following process steps, including poly deposition
In this way, it was possible to accelerate the implementation of necessary modifications, because for a special group of failures a complete new run became unnecessary by mask corrections. This saved time and allowed the introduction of a second test phase for the A1 ASICs of the first preparation.
Second preparation:
• Similar strategy as preparation 1: MPW, six wafers, three stopped before poly.
• Preparation of two ASICs:
- modified ASIC A1 (if necessary)
- ASIC C (complete system with all blocks – see Annex, Fig.1)
3. WP3: Architectural design
Based on the feedback of the specification analysis (WP1) and the results of the feasibility investigations, the specifications were updated and refined regarding the target parameters of the ASIC, the external and internal (i.e. between the blocks) interfaces and timing conditions. In order to check the system functionality, first designs for the functional blocks were done within this workpackage. The following blocks had to be realised:
- 4 independent single-pole, single-throw switches
- DAC + MUX
- Charge amplifier
- ADC (along with gain and offset adaptation stage)
- Thermal probe
- Voltage references
ASIC A1
This ASIC contains only the switches.
ASIC A1 was used to evaluate performances of a DAC+MUX function on SAGEM’s evaluation boards. It offers the possibility to work either with one single switch, or to wire all switches to one system. Fig.4 (see Annex) shows the functional block diagram of ASIC A1. The four switches are totally independent (except for power supplies PVREF, MVREF and DGND, and voltage VLOGIC).
For the ASIC integration a premoulded Narrow SOIC 16 package was selected.
ASIC C
ASIC C contains all functional blocks. It is the basis for the later series version, and is used for the test of the global behaviour and performance.
The DAC and MUX functions which are critical parts of the analogue chain are implemented in the ASIC which will drive the MEMS sensor of the accelerometer. It also processes the MEMS output with a charge amplifier and an ADC. The ADC is preceded by an adaptation stage (in gain and/or offset) to obtain the best range and performances of the ADC.
Voltage references PVREF and MVREF are synthesized by the ASIC itself from a VREF_IN external signal (band-gap or similar). Large external decoupling capacitors are used.
ASIC_C embeds also a digital thermal probe. Additionally, a 14-Bit-Analog-to-Digital-Converter is implemented in ASIC C. It performs 12-bit true analogue to digital conversion of the charge amplifier full-scale range. ASIC C is packaged into a PLCC68 package.
4. WP4/WP5: ASIC Design and Manufacturing / Full ASIC Design
The simulation results of the A1 ASIC including back annotation simulation on layout basis were discussed intensively with SAFRAN. After the design release the manufacturing process started at XFAB. Fig. 6 (see Annex) shows the final ASIC layout.
Within the first Multi Layer Mask Run, two types of ASICs were prepared. The first ASIC (ASIC A1) contains the switches according to the specification of SAFRAN. The second one contains the charge amplifier being part of ASIC C, which was prepared for test purposes.
The originally planned ASIC A2 became obsolete, because the A1 ASIC offers the possibility to work either with one single switch, or to wire all switches to one system. The pinning of both ASICs is identical.
The necessary test boards for both ASICs were designed in parallel to the XFAB fabrication process.
After delivery from XFAB the ASICs were tested. Except one parameter of ASIC A1, both ASICs have the requested functionality. The problem was the power consumption. ASIC A1 works only up to a voltage of +/-7V correctly. When operating with a voltage of +/-9V (as specified) the power consumption exceeds the specified value. After a complex failure analysis, parasitic effects in the layout were detected as reason. Complex design measures were taken to overcome the problem. Because a part of the wafers had been stopped, it was possible to modify the layout on metal mask level and to continue the fabrication of this batch with a modified layout. However, not all modifications could be implemented on metal mask level. That's why remained a design risk. Finally, the modified ASIC A1 did not meet the specification, too.
The complete set of modifications resulting from the failure analysis for ASIC A1 (see Deliverables 4.3 and 4.4) were implemented into the layout of ASIC C. Especially, this concerned all modifications to prevent the parasitic effects. The charge amplifier layout was implemented without modifications. This block works as specified.
ASIC C contains the following main blocks:
• DAC/MUX unit with high performance switches (fully modified according to test results of ASIC A1)
The main components of the DAC and MUX block are the switches. It must be noted that the switches are not simple sub-blocks. With respect to the planned application in avionics, the requirements regarding parameter values (e.g. fall and rise times), stability, power consumption and reliability are highly demanding and bring the CMOS technology to its limits. To meet the specification, a lot of special design measures were necessary which made the design process very complex and time-consuming.
For the several needed supply voltages, tailored transistors with specific characteristics had to be designed and were implemented into the switches. This was the only way to guarantee a stable and equal behaviour for the whole voltage range.
• Charge Amplifier (successful tested version)
The function of the charge amplifier is to measure the modulated charges during detection phases without significant alteration of the wave shapes applied to the electrodes. For the realisation of the charge amplifier different designs were made and simulated. The final version of this block was integrated in a separate test chip. This intermediate step was necessary, because the requested values for bandwidth, voltage swing and settling time are critical parameters.
• Thermal probe
The thermal probe is used for measuring the precise chip temperature. The value is digitalised and stored in a register. Via Interface 2 this register can be read. Two measurement ranges are selectable. According to the specification, the temperature range to be measured is between -55°C and +110°C.
• Integrated A/D Converter
Basis for development of the Analogue to Digital Converter was AMACs own 14bit-ADC (IP block). For the Micro-IMU project it was modified. To comply with the timing requirements and the resolution of true 12 bits, a resolution of 13 bits was calculated.
• Voltage reference
The reference block is another main block of ASIC C. Very high precise voltage references are essential for the operation of both ADCs, the charge amplifier and temperature probe. All internal references and also the voltages MVREF and PVREF are derived from an external reference voltage cell. An external reference source is used because of its better parameters compared to an integrated solution. Furthermore, the derived voltages can be trimmed via the serial interface to compensate offset errors of the amplifiers. As example, Figure 5 shows the effect of modifying the adjustment registers of the upper and lower ADC reference voltage at different temperatures. The normal values are + 500mV for the upper and -500mV for the lower reference. They can be modified in steps of 3.1 mV over a range of +/- 25mV.
The voltages PVREF (+9V) and MVREF (-9V) are also adjustable over a range of 80mV in steps of 5mV.
The originally planned On-chip diagnostic components were not implemented, because all critical points of the circuit can be directly accessed via the ASIC pins.
ASIC C has two interfaces for communication. Because of the high data rates and the real time computing, the Serial Interface 1 is only used for the transmission of the acceleration data. Interface 2 serves for the read out of the measured temperature, and for writing the configuration and adjustment register. To avoid influences between the ADCs, each one has its own references, which can be trimmed separately.
The positive and negative reference voltage of each converter cannot be adjusted separately, because an exact reference voltage range is the most important condition for the correct operation of the ADC (and not its exact limit values).
The basis for the final layout was the developed floorplan (see Annex, Fig. 6). Main criteria to be considered in the design were
• freedom from interferences between the different blocks
• different voltage levels of the blocks
• positions of the pads, especially for the sensor element.
All interface pins are placed on the “east side” of the layout, sensitive analogue ones are not arranged here. The control signals for the switches are on the “west side”. The sensitive charge amplifier pads are located altogether in the north. The TBD marked pads in the floorplan were placed only for reserve purposes in the design phase and don’t have corresponding pads in the layout.
Fig. 7 in the Annex shows the final layout. The resulting behaviour was checked by complex back-annotation simulations.
ASIC C has a size of 4.15 x 3.35 mm² and 51 pads. For testing it will be housed into a CLCC 68 package (ceramic leaded chip carrier).
Because of delays in the manufacturing process for ASIC A1 resulting from the PTRO (Partial Transfer of Rights and Obligations) from GEMAC to AMAC, the time-consuming failure analysis to find the reasons for the parasitic effects and problems in the fabrication process of XFAB it was not possible to test the delivered ASIC C prototypes within the Micro-IMU project. It will be done by AMAC after the official project end at own expense.
The objective is to deliver ASIC C prototypes with full functionality to our CSJU partner SAFRAN in May/June 2017 for a complex system test, and to start the industrialisation process.
Potential Impact:
AMAC will replicate the acquired know-how for sophisticated analogue designs in other customer projects and for the development of own products. This will improve the market position of AMAC and will safeguard the employment in the company.
In case of a correctly working ASIC C, a direct economic benefit will result from the purchase of ASICs to SAFRAN.
Because of the special characteristic of the project (single submission), dissemination activities were not planned. The benefits and potential impact of the developed ASIC can be demonstrated only in the context of the complete MEMS based accelerometer system. Therefore, publications and other dissemination activities will be made by the members of the Cleansky consortium. AMAC will assist if required.
List of Websites:
not applicable
