Description du projet
Prévision innovante de la fiabilité des systèmes électroniques
Afin d’assurer des performances efficaces, il est de la plus haute importance que la fiabilité des systèmes électroniques présente un haut degré de précision. C’est exactement ce que le projet ABSREF, financé par l’UE, chercher à prévoir. Le projet présentera un cadre de simulation innovant sensible au vieillissement et à la charge de travail, qui affiche un temps d’exécution acceptable. Ce cadre générique permettra d’optimiser les performances du système en présence de multiples phénomènes liés au vieillissement, notamment l’instabilité de la température de polarisation négative et positive et l’injection de porteurs chauds. L’amélioration de la marge de synchronisation ou de la bande de garde que ce flux permet d’obtenir devrait contribuer à améliorer davantage la vitesse, la puissance et la durabilité des systèmes électroniques et à réduire leurs coûts.
Objectif
This proposal envisions to foretell the reliability of electronic systems with high degree of accuracy by introducing a novel workload dependent aging aware simulation framework which has acceptable run-time. The framework is generic in nature and will enable one to perform system optimization in presence of multiple aging related phenomena including negative bias temperature instability, positive bias temperature instability, and hot carrier injection. Thus the benefits of the improved timing margin or guard-band incurred by this flow can be leveraged to further improve speed, power, durability of electronic systems and reduce cost. An efficient workload abstraction scheme will be employed which speeds up the transistor level degradation evaluation with accuracy comparable to that of cycle-accurate simulations. Using the device level degradation results, standard cell library characterization will be performed by statistical methods based on Design of Experiments and Response surface Modelling approach. The created workload dependent, aging aware cell libraries will be used to carry out static timing analysis and optimization. Critical path delay degradation evaluated under this framework will be compared with the corner based aging analysis to highlight the impact of the innovation. The framework will be validated using industry standardized, CPU intensive SPEC2006 benchmark suite run on top of multi-core industrial processor. Considering its interdisciplinary nature, the project will help bridge the gap between two disciplines: the device level reliability research and system level interactions. Working in highly international and intersectoral environment of the host IMEC, Dr. Mishra will enhance his professional skills to become a mature independent researcher.
Champ scientifique
Programme(s)
Régime de financement
MSCA-IF-EF-ST - Standard EFCoordinateur
3001 Leuven
Belgique