Description du projet
Former des chercheurs sur les semi-conducteurs III-V
La technologie CMOS est le procédé commercial dominant pour la fabrication de circuits intégrés. Développés en 1960, les premiers procédés CMOS utilisaient le métal comme conducteur de grille. Aujourd’hui, les grilles sont fabriquées en polysilicium. On observe également un glissement vers l’hybridation des fonctions avec l’apport de capteurs, de puissance, de mémoire et de fonctions photoniques sur une même puce. Plus précisément, on s’intéresse de plus en plus à l’intégration de matériaux III-V et d’autres semi-conducteurs complexes qui présentent des avantages par rapport au silicium. Le projet DESIGN-EID, financé par l’UE, relèvera ce défi technologique en étudiant l’impact des défauts sur les performances des dispositifs électroniques et photoniques. Il formera trois chercheurs en début de carrière qui travailleront sur des solutions pour combler le fossé entre les simulations prédictives, les matériaux expérimentaux et le développement de dispositifs.
Objectif
In semiconductor technology and applications today, we are increasingly observing a shift from the pure silicon CMOS technology towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. In particular, there is a great interest in the heterogeneous and monolithic integration of III-V materials and other complex semiconductors, such as III-Nitrides and SiC on Si substrate. However, the direct growth of III-V materials on silicon inevitably will lead to crystal defects that significantly decreases performance of novel devices.
To overcome this main technological challenge and to make this new technology financially viable, the most cost-effective and time-effective approach is to combine experimental and simulation work, which indeed is the main aim on this project – DESING-EID. This will be achieved by addressing the following objectives.
The first objective of DESIGN-EID is to train three young ESRs who will bridge the gap between predictive simulations, experimental materials and device development by developing simulation tools for prediction of crystal growth as a function of process conditions. Secondly, completely eliminating defects in compound semiconductors is likely not achievable, therefore a simulation framework providing an accurate evaluation of their impact on device performance will be essential for designing devices and materials minimizing their impact. Furthermore, semiconductor defects in semiconductors may be exploited for their unique electronic properties if their presence and properties are controlled. For example, vacancies might be used to implement Qu-bits, whereas extended defects, such as dislocations, can provide unique transport properties. Hence, the last objective of the DESIGN-EID project focuses on experimental control and accurate simulation of the impact of defects on electronic and photonic device performance.
Champ scientifique
- engineering and technologymaterials engineeringcrystals
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarequantum computers
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- natural scienceschemical sciencesinorganic chemistrymetalloids
- natural sciencescomputer and information sciencessoftwaresoftware applicationssimulation software
Mots‑clés
Programme(s)
Régime de financement
MSCA-ITN - Marie Skłodowska-Curie Innovative Training Networks (ITN)Coordinateur
G12 8QQ Glasgow
Royaume-Uni