Projektbeschreibung
Die Forschungsgemeinschaft über III-V-Halbleiter aufklären
CMOS ist die vorherrschende kommerzielle Verfahrenstechnik zur Herstellung integrierter Schaltkreise. CMOS-Verfahren wurden 1960 entwickelt und verwendeten ursprünglich Metall als Gateleitung. Heute bestehen die Gates aus Polysilizium. Es gibt auch einen Wandel in Richtung der Hybridisierung von Funktionen in dem Sinne, dass Sensoren-, Stromversorgungs-, Speicher- und Photonikfunktionalitäten auf denselben Chip gebracht werden. Insbesondere besteht immer mehr Interesse an der Integration von III-V-Materialien und anderer komplexer Halbleiter, die gewisse Vorteile im Vergleich zu Silizium haben. Das EU-finanzierte Projekt DESIGN-EID stellt sich der technologischen Herausforderung, indem es die Auswirkungen von Defekten auf die Leistung elektronischer und photonischer Geräte untersucht. Es wird drei Nachwuchsforscherinnen und -forscher ausbilden, um die Lücke zwischen prädiktiven Simulationen, experimentellen Materialien und der Geräteentwicklung zu schließen.
Ziel
In semiconductor technology and applications today, we are increasingly observing a shift from the pure silicon CMOS technology towards hybridisation of function in terms of bringing in sensors, power, memory and photonics functionality on the same chip. In particular, there is a great interest in the heterogeneous and monolithic integration of III-V materials and other complex semiconductors, such as III-Nitrides and SiC on Si substrate. However, the direct growth of III-V materials on silicon inevitably will lead to crystal defects that significantly decreases performance of novel devices.
To overcome this main technological challenge and to make this new technology financially viable, the most cost-effective and time-effective approach is to combine experimental and simulation work, which indeed is the main aim on this project – DESING-EID. This will be achieved by addressing the following objectives.
The first objective of DESIGN-EID is to train three young ESRs who will bridge the gap between predictive simulations, experimental materials and device development by developing simulation tools for prediction of crystal growth as a function of process conditions. Secondly, completely eliminating defects in compound semiconductors is likely not achievable, therefore a simulation framework providing an accurate evaluation of their impact on device performance will be essential for designing devices and materials minimizing their impact. Furthermore, semiconductor defects in semiconductors may be exploited for their unique electronic properties if their presence and properties are controlled. For example, vacancies might be used to implement Qu-bits, whereas extended defects, such as dislocations, can provide unique transport properties. Hence, the last objective of the DESIGN-EID project focuses on experimental control and accurate simulation of the impact of defects on electronic and photonic device performance.
Wissenschaftliches Gebiet
- engineering and technologymaterials engineeringcrystals
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarequantum computers
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- natural scienceschemical sciencesinorganic chemistrymetalloids
- natural sciencescomputer and information sciencessoftwaresoftware applicationssimulation software
Schlüsselbegriffe
Programm/Programme
Thema/Themen
Aufforderung zur Vorschlagseinreichung
Andere Projekte für diesen Aufruf anzeigenFinanzierungsplan
MSCA-ITN - Marie Skłodowska-Curie Innovative Training Networks (ITN)Koordinator
G12 8QQ Glasgow
Vereinigtes Königreich