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CoPackaging of Terabit direct-detection and coherent Optical Engines and switching circuits in mulTI-Chip moduleS for Datacenter networks and the 5G optical fronthaul

Periodic Reporting for period 1 - POETICS (CoPackaging of Terabit direct-detection and coherent Optical Engines and switching circuits in mulTI-Chip moduleS for Datacenter networks and the 5G optical fronthaul)

Berichtszeitraum: 2020-01-01 bis 2021-06-30

POETICS is a 3-year Research and Innovation Action project, started on January 1st, 2020, and comes as a technology/fabrication-intensive project aiming to develop novel Terabit optical engines and optical switching circuits and co-package them with digital switching chips to realize Multi-Chip Modules (MCM) for the next generation switching equipment with Tb/s capacities and very high energy efficiency that fit into the roadmap of vendors.
To achieve this, POETICS is relying on a photonic integration technology based on a silicon nitride platform, optical polymers, InP electro-absorption modulated lasers (EMLs) and external cavity lasers, and on high-speed electronics based on BiCMOS technology.
Specific target in POETICS is the development of six (6) prototypes:
• MCM with 1.6 Tb/s OEs and PolyBoard with parallel SMFs on par with the PSM/DR spec for intra-DC connectivity.
• MCM with 1.6 Tb/s OEs and 3D PolyBoard with duplex MCFs for 5G optical fronthaul applications.
• Low-power-consumption 3D Benes Optical Switch
• MCM coherent 64Gbaud OEs with up to 600 Gb/s capacity for DC interconnect applications.
Within the first 18 months, POETICS has noted significant progress towards the project objectives considering that the pandemic crisis has been affecting the project already from M03 onwards. In brief:

Under WP2, POETICS focused on identifying interesting application scenarios for the deployment of POETICS Terabit and optical switches in optical networks and intra-DC networks. The most relevant trends in different Data Centers and network architectures have been also studied, and meaningful use cases for the deployment of the coherent transceivers identified. The high-level requirements and specifications of POETICS optical engines were refined, and extended, tailored for the different network applications. In parallel the design concepts, rules and packaging strategies and methodologies that will be followed for the integration/packaging of POETICS prototypes have been defined. Finally, system-level simulation models for evaluating the transmission performance of the Terabit MCMs and coherent transceivers have been developed and evaluated and basic DSP algorithms have been tested.

Within WP3, the design and fabrication of the 1st generation InP photonic components (EML, phase section and photodiode arrays) are completed. Additionally, the 2D PolyBoards for the first two prototypes (POE-1, -2), have been designed and fabricated and they are under characterization. Simulations for the 3D PolyBoard MCF interposer of POE-3 were performed, and the design of the respective mask set started. In parallel, simulation studies and the design of the fundamental active switching block of the 3D PolyBoard of the optical switch (POE-4) were performed and a mask set was produced and fabrication started. Finally, significant progress has been achieved on the design of the coherent MCMs prototypes (POE-5, -6) and the development of their photonic components and motherboards. Narrow bandwidth tunable external cavity lasers have been developed on the TriPleX platform and tested while the design of the 2D PolyBoard and 2D TriPleX motherboards of POE-5, has been completed and their fabrication started.

Within WP4, the development of the high-bandwidth SiGe BiCMOS electronics started with a thorough analysis of the demonstrator and system requirements in order to assess the architectural and technological challenges and to define the required circuit functions, interfaces and detailed specifications. The quad TIA chip has been designed and is in fabrication whereas significant progress has been made on the more complex AMUX-DRV and ADEMUX chips, including one patent application. Furthermore, the key challenges with regards to interaction of the commercial DSP ASIC for data generation with the project’s SiGe BiCMOS electronics were identified. Early access to evaluation samples of two different 800G DSP designs has been secured, and the most mature ASIC was successfully tested.

Under WP5, the floor plan of the final coherent transceiver (POE-6) and the flip-chip integration techniques were defined. In parallel the component specifications (in terms of physical sizes and geometries) and layouts of the Terabit MCMs prototypes were collected and the individual component interfaces, and device interconnections were defined and finalized. The mechanical setup and PIC configuration are defined, 3D models have been generated and the integration/assembly steps of the MCM prototypes are ready to be applied.

Within WP6, the testing methodologies for the components and the prototypes have been defined for both lab settings and system settings. The most important component parameters that need to be characterized have been identified and the KPIs for the system tests have also been defined. In addition, a first version of the control electronics for the operation of POE-4 (optical switch) and POE-5 (coherent transceiver) prototypes have been developed as open platforms using commercial evaluation boards, commercial laser diode drivers and custom current sources.

Finally, in the context of WP7, POETICS partners carried out exploitation planning activities and MLNX initiated market analysis and regularly updated the consortium on its findings. In parallel and linked to the exploitation strategy, the external advancements in the related state-of-the-art to identify threats to POETICS novelties has been in continuous monitoring and newly generated IP within the project is identified, reported and protected. During the first project period, one European patent was applied. On the communication and dissemination front, extroversion was exercised through the project’s website and social media, and participating in major virtual events (e.g. conferences, workshops, webinars etc.).
The strategic objective of POETICS is to develop the underlying technology in Europe for the next generation datacenters, following an holistic approach to the development of MCM switching devices with Terabit interfaces and optical switching circuits for interconnections inside DC networks and DC interconnects up to 120 km in the metro/regional, based on a synergy of the best performing technologies and components.
POETICS “impact strategy” is aligned with the European industrial leadership in photonic systems integration and interconnect technologies and applications with main focus on i) the development of multifunctional components and hybrid electronic-photonic integration approaches which will allow for global optimization of the system and ii) the development of advanced integration methods and automated assembly processes with simple and reliable steps, high fabrication yield and compatibility with high volume fabrication runs.
During the first 18 months of the project, POETICS partners have already started to successfully leverage the know-how and the tangible results of the project: a unique design for the transmitter SiGe electronics with combined functionality, consisting of a 100Gbaud driver front-end co-integrated with a MUX and clock management was developed; process improvements on the development of active components and hybrid integration that increase yield and lower costs have already been successfully demonstrated; expertise is being built around hybrid assembly processes to name a few.
Artistic layout of the co-packaged MCM