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Novel approach to Area selective Deposition for BEOL Interconnect Applications

Project description

A new approach to nanoscale patterning

Nanoscale patterning of materials is becoming crucial for many devices, especially in the back end of line. Given Intel’s latest 10 nm node, new ways of mastering selective deposition of materials at the nanoscale need to be developed. Selective deposition may lead to a paradigm shift in patterning at future semiconductor technology nodes. With this in mind, the EU-funded NADIA project aims to demonstrate spatial control over a deposited thin film. To do this, it will make use of area-selective deposition (ASD) by atomic layer deposition. This has a number of possible benefits for future device processing and can help to overcome process integration challenges at the sub-10 nm nodes.

Objective

The need for area selective deposition (ASD): Nanoscale patterning of materials is becoming a key issue for a broad range of devices, especially
in the back end of line (BEOL). With the introduction of Intel’s latest 10nm node earlier this year, it is vital to develop new ways to master selective
deposition of materials at the nanoscale, preferably without the use of lithographic and etching steps, as they can be time-consuming, expensive
and mainly subtractive processes. Novel concepts are thus needed to enhance local deposition while decreasing the use of expensive
technological steps. Selective deposition is expected to lead to a paradigm shift in patterning at future semiconductor technology nodes. Area
Selective Deposition (ASD) by ALD brings several potential benefits for future device processing and provides a route to overcome process
integration challenges at the sub 10 nm nodes, i.e. overlay and lithographic misalignment related issues both in the front end of line (FEOL) and
back end of line (BEOL) schemes. Essentially, what ASD gives is spatial control over a deposited thin film. This is the objective of the innovative
NADIA proposal which is now a very relevant topic.

Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Net EU contribution
€ 178 320,00
Address
KAPELDREEF 75
3001 Leuven
Belgium

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Region
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Activity type
Research Organisations
Links
Total cost
€ 178 320,00