Project description DEENESFRITPL Ensuring hardware security and reliability in electronic design automation tools Data protection is not the only concern for cybersecurity; hardware attacks can have equally deleterious effects. Delayed or faulty trafficking of data within hardware components can have serious, even life-threatening consequences: for the Internet of Things, self-driving cars and remote medicine, reliability is one of the primary concerns. Hardware accelerators are increasingly used to meet the demands of cutting-edge technologies. They offload certain tasks onto specialised hardware elements to enhance efficiency compared to using a general-purpose CPU alone. High level synthesis (HLS), an electronic design automation (EDA) tool, takes high-level functional descriptions of a design and turns it into a register-transfer level (RTL) design. The EU-funded SecuReHLS project is developing EDA tools that will enable the rational and automated insertion of protections during an HLS flow to automatically obtain secure and reliable RTL descriptions. Show the project objective Hide the project objective Objective System on Chip (SoC) and Internet of Things (IoT) hardware accelerators are increasingly used in secure and critical applications, such as medical and automotive. For this reason, they need to have high levels of security and reliability at the same time. Hardware attacks are a serious threat for the security of hardware accelerators. Among them, Fault Attacks and Side Channel Attacks can breach even protected devices. Furthermore, injection of errors due to harsh environments may even lead to catastrophic failures of such accelerators. These threats are usually not concurrently addressed since their corresponding protections are not always compatible to each other. In a context, where designers use High Level Synthesis (HLS) flows to increase the productivity of designing hardware accelerators they must also ensure that security and reliability protections are taken into account by the HLS tools.In order to enable HLS flows to be the flow of choice for secure and reliable devices, we propose to provide to SoC and IoT designers, Electronic Design Automation (EDA) tools, capable to evaluate, improve and automate the insertion of protections during an HLS flow. Initially we will study the effects of HLS flows on the synthesis of manually protected high level descriptions. Afterwards, we will address concurrently security and reliability by automating the integration of compatible, countermeasures and mitigation techniques, inside the HLS flow, so as to automatically obtain secure and reliable RTL descriptions. Such tools and methodologies will help to minimize the corresponding overheads for protecting against each threat, while at the same time they will maintain the productivity of the HLS flow at high levels during the design of secure and reliable hardware accelerators. Fields of science natural sciencescomputer and information sciencesinternetinternet of thingssocial sciencessociologyindustrial relationsautomationsocial scienceseconomics and businesseconomicsproduction economicsproductivity Programme(s) H2020-EU.1.3. - EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions Main Programme H2020-EU.1.3.2. - Nurturing excellence by means of cross-border and cross-sector mobility Topic(s) MSCA-IF-2019 - Individual Fellowships Call for proposal H2020-MSCA-IF-2019 See other projects for this call Funding Scheme MSCA-IF - Marie Skłodowska-Curie Individual Fellowships (IF) Coordinator UNIVERSITY OF PIRAEUS RESEARCH CENTER Net EU contribution € 165 085,44 Address Al. papanastasiou 91 185 33 Piraeus Greece See on map Region Αττική Aττική Πειραιάς Activity type Higher or Secondary Education Establishments Links Contact the organisation Opens in new window Website Opens in new window Participation in EU R&I programmes Opens in new window HORIZON collaboration network Opens in new window Other funding € 0,00
