Skip to main content

EDA tools for Secure and Reliable High Level Synthesis Implementations

Project description

Ensuring hardware security and reliability in electronic design automation tools

Data protection is not the only concern for cybersecurity; hardware attacks can have equally deleterious effects. Delayed or faulty trafficking of data within hardware components can have serious, even life-threatening consequences: for the Internet of Things, self-driving cars and remote medicine, reliability is one of the primary concerns. Hardware accelerators are increasingly used to meet the demands of cutting-edge technologies. They offload certain tasks onto specialised hardware elements to enhance efficiency compared to using a general-purpose CPU alone. High level synthesis (HLS), an electronic design automation (EDA) tool, takes high-level functional descriptions of a design and turns it into a register-transfer level (RTL) design. The EU-funded SecuReHLS project is developing EDA tools that will enable the rational and automated insertion of protections during an HLS flow to automatically obtain secure and reliable RTL descriptions.

Call for proposal

H2020-MSCA-IF-2019
See other projects for this call

Funding Scheme

MSCA-IF-EF-ST - Standard EF

Coordinator

KENTRO EREVNON PANEPISTIMIOU PEIRAIOS
Address
Al. Papanastasiou 91
185 33 Peiraias
Greece
Activity type
Higher or Secondary Education Establishments
EU contribution
€ 165 085,44