Descrizione del progetto
Emulare trilioni di operazioni al secondo per ottenere la giusta produzione di chip al primo tentativo
La produzione di chip è un processo complesso e costoso anche quando tutto va alla perfezione. La prototipazione di chip fisici per la rilevazione degli errori e l’ottimizzazione è stata supportata negli ultimi anni dall’uso di field programmable gate array (FPGA). Gli FPGA sono dispositivi a semiconduttore con blocchi logici configurabili che permettono sia una programmazione massicciamente parallela, sia la capacità di riprogrammarli innumerevoli volte fino a quando il progetto è privo di bug e la produzione può iniziare. Si adattano perfettamente allo sviluppo efficiente ed economico dei futuri computer a esascala. Il progetto MEEP, finanziato dall’UE, sta sviluppando una piattaforma di emulazione flessibile basata su FPGA per la co-progettazione e l’integrazione di software e hardware, sostenendo la supremazia europea nel calcolo a esascala e non solo.
Obiettivo
The MareNostrum Experimental Exascale Platform (MEEP) is a flexible FPGA-based emulation platform that will explore hardware/software co-designs for Exascale Supercomputers and other hardware targets, based on European-developed IP. MEEP provides two very important functions: 1) An evaluation platform of pre-silicon IP and ideas, at speed and scale and 2) A software development and experimentation platform to enable software readiness for new hardware. MEEP enables software development, accelerating software maturity, compared to the limitations of software simulation. IP can be tested and validated before moving to silicon, saving time and money.
The objectives of MEEP are to leverage and extend projects like EPI and the POP2 CoE in the following ways:
● Define, develop, and deploy an FPGA-based emulation platform targeting European-based Exascale Supercomputer RISC-V-based IP development, especially hardware/software co-design.
● Develop a base FPGA shell that provides memory and I/O connectivity to the host CPU and other FPGAs.
● Build FPGA tools and support to map enhanced EPI and MEEP IP into the FPGA core, validating and demonstrating European IP.
● Develop the software toolchain (compiler, debugger, profiler, OS, and drivers) for RISC-V based accelerators to enable application development and porting.
MEEP will deliver a series of Open-Source IPs, when possible, that can be used for academic purposes and integrated into a functional accelerator or cores for traditional and emerging HPC applications. This is an exciting target for IPs generated from projects like EPI, and an IP source for follow-on projects as well. MEEP will provide a foundation for building European-based chips and infrastructure to enable rapid prototyping using a library of IPs and a standard set of interfaces to the Host CPU and other FPGAs in the system using the FPGA shell. In addition to RISC-V architecture and hardware ecosystem improvements.
Campo scientifico
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarecomputer processors
- natural sciencescomputer and information sciencessoftwaresoftware development
- natural sciencesbiological sciencesecologyecosystems
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwaresupercomputers
- natural scienceschemical sciencesinorganic chemistrymetalloids
Programma(i)
Meccanismo di finanziamento
RIA - Research and Innovation actionCoordinatore
08034 Barcelona
Spagna