European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem

Project Information

eProcessor

Grant agreement ID: 956702

DOI

10.3030/956702

Project closed

EC signature date 2 December 2020

Start date 1 April 2021

End date 31 March 2025

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost

€ 7 999 975,00

EU contribution

€ 3 999 987,51

Coordinated by

BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
Spain

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Documents, reports (4)

Project Management and Quality Guidelines
Dissemination and communication plan and Exploitation strategy
Simulation infrastructure and early architectural explorations
Dissemination and communication report

Demonstrators, pilots, prototypes (2)

FPGA emulation of single-core system
FPGA emulation of multi-core system and accelerators

Open Research Data Pilot (1)

Data Management Plan (DMP)

Data Management Plan DMP

Other (4)

Release of the O/S, boot environment, compiler and performance tools for the FPGA-based single core system
Initial porting of the use case
FPGA emulation infrastructure and development environment
Microbenchmarks suite to drive design optimizations

Publications

Peer reviewed articles (2)

Efficient Edge AI for Next Generation Smart Mirror Applications

Author(s): Nils Kucza, Florian Porrmann, Christian Stollenwerk, Jens Hagemeyer
Published in: IEEE Access, Issue 13, 2025, Page(s) 93755-93774, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2025.3574492

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Author(s): Jing Chen; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs
Published in: Transactions on Architecture and Code Optimization (1544-3566) vol.19(2022), Issue 6, 2022, ISSN 1544-3566
Publisher: Association for Computing Machinary, Inc.
DOI: 10.48550/arxiv.2201.12186

Conference proceedings (12)

eProcessor

Author(s): Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto Gonzalez, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vasilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavish
Published in: Proceedings of the 20th ACM International Conference on Computing Frontiers, 2024, Page(s) 309-314, ISBN 979-8-4007-0140-5
Publisher: ACM
DOI: 10.1145/3587135.3592178

SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs

Author(s): Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
Published in: 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2024, Page(s) 325-336, ISBN 979-8-3503-8712-4
Publisher: IEEE
DOI: 10.1109/ipdps57955.2024.00036

FastTrackNoC: A NoC with FastTrack Router Datapaths

Author(s): A. Ejaz and I. Sourdis
Published in: IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, 2022, Page(s) 971-985
Publisher: IEEE
DOI: 10.1109/hpca53966.2022.00075

GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment

Author(s): Max Doblas, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova-Musté, Christopher Frances Batten, Santiago Marco-Sola, Miquel Moretó
Published in: 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023, Page(s) 1466-1480, ISBN 979-8-4007-0329-4
Publisher: ACM
DOI: 10.1145/3613424.3614306

Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs

Author(s): Miquel Moreto Santiago Marco-Sola
Published in: 4th HPC Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), 2022, Page(s) 1
Publisher: IEEE

VSA: A Hybrid Vector-Systolic Architecture

Author(s): Mateo Vazquez Maceiras, Muhammad Waqar Azhar, Pedro Trancoso
Published in: 2022 IEEE 40th International Conference on Computer Design (ICCD), 2023, Page(s) 368-376
Publisher: IEEE
DOI: 10.1109/iccd56317.2022.00061

RECS: A Scalable Platform for Heterogeneous Computing

Author(s): Kevin Mika, Florian Porrmann, Nils Kucza, René Griessl, Jens Hagemeyer
Published in: 2023 IEEE 36th International System-on-Chip Conference (SOCC), 2023, Page(s) 1-6, ISBN 979-8-3503-0011-6
Publisher: IEEE
DOI: 10.1109/socc58585.2023.10256982

Reusable Verification Environment for a RISC-V Vector Accelerator

Author(s): Quiroga, Josue; Genovese, Roberto Ignacio; Díaz, Ivan; Yano, Henrique; Ali, Asif; Sommez, Nehir; Palomar Pérez, Óscar; JImenez, Victor; Rodriguez, Mario; Dominguez, Marc
Published in: instname:Universitat Politècnica de Catalunya (UPC), Issue 1, 2023, Page(s) 1-8
Publisher: Accellera Systems Initiative (Accellera)

FPGA checkpointing for scientific computing

Author(s): Perelló Bacardit, Marc; Bautista Gomez, Leonardo; Unsal, Osman Sabri
Published in: IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, ISBN 978-1-6654-3370-9
Publisher: IEEE
DOI: 10.1109/iolts52814.2021.9486693

Exploiting the Potential of Flexible Processing Units

Author(s): Mateo Vázquez, Muhammad Waqar Azhar, Pedro Trancoso
Published in: 2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2023, Page(s) 34-45, ISBN 979-8-3503-0549-4
Publisher: IEEE
DOI: 10.1109/sbac-pad59825.2023.00013

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Author(s): Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, Miquel Pericas
Published in: 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2023, ISBN 978-1-6654-5156-7
Publisher: IEEE
DOI: 10.1109/sbac-pad55451.2022.00043

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency

Author(s): Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
Published in: Proceedings of the 52nd International Conference on Parallel Processing, 2024, Page(s) 828-838, ISBN 979-8-4007-0843-5
Publisher: ACM
DOI: 10.1145/3605573.3605586

Thesis and dissertations (2)

Energy Efficient Task Mapping and Resource Management on Multi-core Architectures

Author(s): Chen, Jing
Published in: Issue 4, 2022
Publisher: Sweden

Adaptive Task Scheduling and Resource Management Techniques for Improving Energy Efficiency on Multi-core Systems

Author(s): Chen, Jing
Published in: Thesis/Dissertation, Issue 1, 2024
Publisher: Sweden