European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem

Informazioni relative al progetto

eProcessor

ID dell’accordo di sovvenzione: 956702

DOI 10.3030/956702

Data della firma CE 2 Dicembre 2020

Data di avvio 1 Aprile 2021

Data di completamento 31 Marzo 2025

Finanziato da

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Costo totale € 7 999 975,00

Contributo UE € 3 999 987,51

Coordinato da

BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
Spain

Risultati finali

Documents, reports (4)

Project Management and Quality Guidelines
Dissemination and communication plan and Exploitation strategy
Simulation infrastructure and early architectural explorations
Dissemination and communication report

Demonstrators, pilots, prototypes (1)

FPGA emulation of single-core system

Open Research Data Pilot (1)

Data Management Plan (DMP)

Data Management Plan DMP

Other (2)

Release of the O/S, boot environment, compiler and performance tools for the FPGA-based single core system
Initial porting of the use case

Pubblicazioni

Conference proceedings (4)

FastTrackNoC: A NoC with FastTrack Router Datapaths

Autori: A. Ejaz and I. Sourdis
Pubblicato in: IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, 2022, Pagina/e 971-985
Editore: IEEE
DOI: 10.1109/hpca53966.2022.00075

Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs

Autori: Miquel Moreto Santiago Marco-Sola
Pubblicato in: 4th HPC Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), 2022, Pagina/e 1
Editore: IEEE

FPGA checkpointing for scientific computing

Autori: Perelló Bacardit, Marc; Bautista Gomez, Leonardo; Unsal, Osman Sabri
Pubblicato in: IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, ISBN 978-1-6654-3370-9
Editore: IEEE
DOI: 10.1109/iolts52814.2021.9486693

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Autori: Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas
Pubblicato in: IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022), 2022
Editore: IEEE

Peer reviewed articles (1)

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Autori: Jing Chen; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs
Pubblicato in: Transactions on Architecture and Code Optimization (1544-3566) vol.19(2022), Numero 15443566, 2022, ISSN 1544-3566
Editore: Association for Computing Machinary, Inc.
DOI: 10.48550/arxiv.2201.12186