European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem

Informazioni relative al progetto

eProcessor

ID dell’accordo di sovvenzione: 956702

DOI

10.3030/956702

Progetto chiuso

Data della firma CE 2 Dicembre 2020

Data di avvio 1 Aprile 2021

Data di completamento 31 Marzo 2025

Finanziato da

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Costo totale

€ 7 999 975,00

Contributo UE

€ 3 999 987,51

Coordinato da

BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
Spain

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Documents, reports (4)

Project Management and Quality Guidelines
Dissemination and communication plan and Exploitation strategy
Simulation infrastructure and early architectural explorations
Dissemination and communication report

Demonstrators, pilots, prototypes (2)

FPGA emulation of single-core system
FPGA emulation of multi-core system and accelerators

Open Research Data Pilot (1)

Data Management Plan (DMP)

Data Management Plan DMP

Other (4)

Release of the O/S, boot environment, compiler and performance tools for the FPGA-based single core system
Initial porting of the use case
FPGA emulation infrastructure and development environment
Microbenchmarks suite to drive design optimizations

Pubblicazioni

Peer reviewed articles (2)

Efficient Edge AI for Next Generation Smart Mirror Applications

Autori: Nils Kucza, Florian Porrmann, Christian Stollenwerk, Jens Hagemeyer
Pubblicato in: IEEE Access, Numero 13, 2025, Pagina/e 93755-93774, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2025.3574492

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Autori: Jing Chen; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs
Pubblicato in: Transactions on Architecture and Code Optimization (1544-3566) vol.19(2022), Numero 6, 2022, ISSN 1544-3566
Editore: Association for Computing Machinary, Inc.
DOI: 10.48550/arxiv.2201.12186

Conference proceedings (12)

eProcessor

Autori: Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto Gonzalez, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vasilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavish
Pubblicato in: Proceedings of the 20th ACM International Conference on Computing Frontiers, 2024, Pagina/e 309-314, ISBN 979-8-4007-0140-5
Editore: ACM
DOI: 10.1145/3587135.3592178

SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs

Autori: Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
Pubblicato in: 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2024, Pagina/e 325-336, ISBN 979-8-3503-8712-4
Editore: IEEE
DOI: 10.1109/ipdps57955.2024.00036

FastTrackNoC: A NoC with FastTrack Router Datapaths

Autori: A. Ejaz and I. Sourdis
Pubblicato in: IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, 2022, Pagina/e 971-985
Editore: IEEE
DOI: 10.1109/hpca53966.2022.00075

GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment

Autori: Max Doblas, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova-Musté, Christopher Frances Batten, Santiago Marco-Sola, Miquel Moretó
Pubblicato in: 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023, Pagina/e 1466-1480, ISBN 979-8-4007-0329-4
Editore: ACM
DOI: 10.1145/3613424.3614306

Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs

Autori: Miquel Moreto Santiago Marco-Sola
Pubblicato in: 4th HPC Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), 2022, Pagina/e 1
Editore: IEEE

VSA: A Hybrid Vector-Systolic Architecture

Autori: Mateo Vazquez Maceiras, Muhammad Waqar Azhar, Pedro Trancoso
Pubblicato in: 2022 IEEE 40th International Conference on Computer Design (ICCD), 2023, Pagina/e 368-376
Editore: IEEE
DOI: 10.1109/iccd56317.2022.00061

RECS: A Scalable Platform for Heterogeneous Computing

Autori: Kevin Mika, Florian Porrmann, Nils Kucza, René Griessl, Jens Hagemeyer
Pubblicato in: 2023 IEEE 36th International System-on-Chip Conference (SOCC), 2023, Pagina/e 1-6, ISBN 979-8-3503-0011-6
Editore: IEEE
DOI: 10.1109/socc58585.2023.10256982

Reusable Verification Environment for a RISC-V Vector Accelerator

Autori: Quiroga, Josue; Genovese, Roberto Ignacio; Díaz, Ivan; Yano, Henrique; Ali, Asif; Sommez, Nehir; Palomar Pérez, Óscar; JImenez, Victor; Rodriguez, Mario; Dominguez, Marc
Pubblicato in: instname:Universitat Politècnica de Catalunya (UPC), Numero 1, 2023, Pagina/e 1-8
Editore: Accellera Systems Initiative (Accellera)

FPGA checkpointing for scientific computing

Autori: Perelló Bacardit, Marc; Bautista Gomez, Leonardo; Unsal, Osman Sabri
Pubblicato in: IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, ISBN 978-1-6654-3370-9
Editore: IEEE
DOI: 10.1109/iolts52814.2021.9486693

Exploiting the Potential of Flexible Processing Units

Autori: Mateo Vázquez, Muhammad Waqar Azhar, Pedro Trancoso
Pubblicato in: 2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2023, Pagina/e 34-45, ISBN 979-8-3503-0549-4
Editore: IEEE
DOI: 10.1109/sbac-pad59825.2023.00013

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Autori: Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, Miquel Pericas
Pubblicato in: 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2023, ISBN 978-1-6654-5156-7
Editore: IEEE
DOI: 10.1109/sbac-pad55451.2022.00043

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency

Autori: Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
Pubblicato in: Proceedings of the 52nd International Conference on Parallel Processing, 2024, Pagina/e 828-838, ISBN 979-8-4007-0843-5
Editore: ACM
DOI: 10.1145/3605573.3605586

Thesis and dissertations (2)

Energy Efficient Task Mapping and Resource Management on Multi-core Architectures

Autori: Chen, Jing
Pubblicato in: Numero 4, 2022
Editore: Sweden

Adaptive Task Scheduling and Resource Management Techniques for Improving Energy Efficiency on Multi-core Systems

Autori: Chen, Jing
Pubblicato in: Thesis/Dissertation, Numero 1, 2024
Editore: Sweden