European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem

Informacje na temat projektu

eProcessor

Identyfikator umowy o grant: 956702

DOI 10.3030/956702

Data podpisania przez KE 2 Grudnia 2020

Data rozpoczęcia 1 Kwietnia 2021

Data zakończenia 31 Marca 2025

Finansowanie w ramach

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Koszt całkowity € 7 999 975,00

Wkład UE € 3 999 987,51

Koordynowany przez

BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
Spain

Rezultaty

Documents, reports (4)

Project Management and Quality Guidelines
Dissemination and communication plan and Exploitation strategy
Simulation infrastructure and early architectural explorations
Dissemination and communication report

Demonstrators, pilots, prototypes (1)

FPGA emulation of single-core system

Open Research Data Pilot (1)

Data Management Plan (DMP)

Data Management Plan DMP

Other (2)

Release of the O/S, boot environment, compiler and performance tools for the FPGA-based single core system
Initial porting of the use case

Publikacje

Conference proceedings (4)

FastTrackNoC: A NoC with FastTrack Router Datapaths

Autorzy: A. Ejaz and I. Sourdis
Opublikowane w: IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, 2022, Strona(/y) 971-985
Wydawca: IEEE
DOI: 10.1109/hpca53966.2022.00075

Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs

Autorzy: Miquel Moreto Santiago Marco-Sola
Opublikowane w: 4th HPC Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), 2022, Strona(/y) 1
Wydawca: IEEE

FPGA checkpointing for scientific computing

Autorzy: Perelló Bacardit, Marc; Bautista Gomez, Leonardo; Unsal, Osman Sabri
Opublikowane w: IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, ISBN 978-1-6654-3370-9
Wydawca: IEEE
DOI: 10.1109/iolts52814.2021.9486693

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Autorzy: Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas
Opublikowane w: IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022), 2022
Wydawca: IEEE

Peer reviewed articles (1)

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Autorzy: Jing Chen; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs
Opublikowane w: Transactions on Architecture and Code Optimization (1544-3566) vol.19(2022), Numer 15443566, 2022, ISSN 1544-3566
Wydawca: Association for Computing Machinary, Inc.
DOI: 10.48550/arxiv.2201.12186